diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-adc.adb b/arch/ARM/STM32/devices/stm32f401/stm32-adc.adb new file mode 100644 index 000000000..c6f234fed --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-adc.adb @@ -0,0 +1,898 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2017, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_adc.c -- +-- @author MCD Application Team -- +-- @version V1.3.1 -- +-- @date 25-March-2015 -- +-- @brief Header file of ADC HAL module. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +with STM32_SVD.ADC; use STM32_SVD.ADC; + +package body STM32.ADC is + + procedure Set_Sequence_Position + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Regular_Channel_Rank) + with Inline; + + procedure Set_Sampling_Time + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Sample_Time : Channel_Sampling_Times) + with Inline; + + procedure Set_Injected_Channel_Sequence_Position + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Injected_Channel_Rank) + with Inline; + + procedure Set_Injected_Channel_Offset + (This : in out Analog_To_Digital_Converter; + Rank : Injected_Channel_Rank; + Offset : Injected_Data_Offset) + with Inline; + + ------------ + -- Enable -- + ------------ + + procedure Enable (This : in out Analog_To_Digital_Converter) is + begin + if not This.CR2.ADON then + This.CR2.ADON := True; + delay until Clock + ADC_Stabilization; + end if; + end Enable; + + ------------- + -- Disable -- + ------------- + + procedure Disable (This : in out Analog_To_Digital_Converter) is + begin + This.CR2.ADON := False; + end Disable; + + ------------- + -- Enabled -- + ------------- + + function Enabled (This : Analog_To_Digital_Converter) return Boolean is + (This.CR2.ADON); + + ---------------------- + -- Conversion_Value -- + ---------------------- + + function Conversion_Value + (This : Analog_To_Digital_Converter) + return UInt16 + is + begin + return This.DR.DATA; + end Conversion_Value; + + --------------------------- + -- Data_Register_Address -- + --------------------------- + + function Data_Register_Address + (This : Analog_To_Digital_Converter) + return System.Address + is + (This.DR'Address); + + ------------------------------- + -- Injected_Conversion_Value -- + ------------------------------- + + function Injected_Conversion_Value + (This : Analog_To_Digital_Converter; + Rank : Injected_Channel_Rank) + return UInt16 + is + begin + case Rank is + when 1 => + return This.JDR1.JDATA; + when 2 => + return This.JDR2.JDATA; + when 3 => + return This.JDR3.JDATA; + when 4 => + return This.JDR4.JDATA; + end case; + end Injected_Conversion_Value; + + -------------------- + -- Configure_Unit -- + -------------------- + + procedure Configure_Unit + (This : in out Analog_To_Digital_Converter; + Resolution : ADC_Resolution; + Alignment : Data_Alignment) + is + begin + This.CR1.RES := ADC_Resolution'Enum_Rep (Resolution); + This.CR2.ALIGN := Alignment = Left_Aligned; + end Configure_Unit; + + ------------------------ + -- Current_Resolution -- + ------------------------ + + function Current_Resolution + (This : Analog_To_Digital_Converter) + return ADC_Resolution + is (ADC_Resolution'Val (This.CR1.RES)); + + ----------------------- + -- Current_Alignment -- + ----------------------- + + function Current_Alignment + (This : Analog_To_Digital_Converter) + return Data_Alignment + is ((if This.CR2.ALIGN then Left_Aligned else Right_Aligned)); + + --------------------------------- + -- Configure_Common_Properties -- + --------------------------------- + pragma Warnings (Off, "formal parameter ""Mode"" is not referenced"); + procedure Configure_Common_Properties + (Mode : Multi_ADC_Mode_Selections; + Prescalar : ADC_Prescalars; + DMA_Mode : Multi_ADC_DMA_Modes; + Sampling_Delay : Sampling_Delay_Selections) + is + pragma Warnings (On, "formal parameter ""Mode"" is not referenced"); + -- We ignore this warning to conform to the common spec in STM32 + -- family + begin + ADC_Common_Periph.CCR.DELAY_k := + Sampling_Delay_Selections'Enum_Rep (Sampling_Delay); + ADC_Common_Periph.CCR.DMA := Multi_ADC_DMA_Modes'Enum_Rep (DMA_Mode); + ADC_Common_Periph.CCR.ADCPRE := ADC_Prescalars'Enum_Rep (Prescalar); + end Configure_Common_Properties; + + ----------------------------------- + -- Configure_Regular_Conversions -- + ----------------------------------- + + procedure Configure_Regular_Conversions + (This : in out Analog_To_Digital_Converter; + Continuous : Boolean; + Trigger : Regular_Channel_Conversion_Trigger; + Enable_EOC : Boolean; + Conversions : Regular_Channel_Conversions) + is + begin + This.CR2.EOCS := Enable_EOC; + This.CR2.CONT := Continuous; + + This.CR1.SCAN := Conversions'Length > 1; + + if Trigger.Enabler /= Trigger_Disabled then + This.CR2.EXTSEL := External_Events_Regular_Group'Enum_Rep (Trigger.Event); + This.CR2.EXTEN := External_Trigger'Enum_Rep (Trigger.Enabler); + else + This.CR2.EXTSEL := 0; + This.CR2.EXTEN := 0; + end if; + + for Rank in Conversions'Range loop + declare + Conversion : Regular_Channel_Conversion renames Conversions (Rank); + begin + Configure_Regular_Channel + (This, Conversion.Channel, Rank, Conversion.Sample_Time); + + -- We check the VBat first because that channel is also used for + -- the temperature sensor channel on some MCUs, in which case the + -- VBat conversion is the only one done. This order reflects that + -- hardware behavior. + if VBat_Conversion (This, Conversion.Channel) then + Enable_VBat_Connection; + elsif VRef_TemperatureSensor_Conversion (This, Conversion.Channel) + then + Enable_VRef_TemperatureSensor_Connection; + end if; + end; + end loop; + + This.SQR1.L := UInt4 (Conversions'Length - 1); -- biased rep + end Configure_Regular_Conversions; + + ------------------------------------ + -- Configure_Injected_Conversions -- + ------------------------------------ + + procedure Configure_Injected_Conversions + (This : in out Analog_To_Digital_Converter; + AutoInjection : Boolean; + Trigger : Injected_Channel_Conversion_Trigger; + Enable_EOC : Boolean; + Conversions : Injected_Channel_Conversions) + is + begin + This.CR2.EOCS := Enable_EOC; + + -- Injected channels cannot be converted continuously. The only + -- exception is when an injected channel is configured to be converted + -- automatically after regular channels in continuous mode. See note in + -- RM 13.3.5, pg 390, and "Auto-injection" section on pg 392. + This.CR1.JAUTO := AutoInjection; + + if Trigger.Enabler /= Trigger_Disabled then + This.CR2.JEXTEN := External_Trigger'Enum_Rep (Trigger.Enabler); + This.CR2.JEXTSEL := External_Events_Injected_Group'Enum_Rep (Trigger.Event); + else + This.CR2.JEXTEN := 0; + This.CR2.JEXTSEL := 0; + end if; + + for Rank in Conversions'Range loop + declare + Conversion : Injected_Channel_Conversion renames + Conversions (Rank); + begin + Configure_Injected_Channel + (This, + Conversion.Channel, + Rank, + Conversion.Sample_Time, + Conversion.Offset); + + -- We check the VBat first because that channel is also used for + -- the temperature sensor channel on some MCUs, in which case the + -- VBat conversion is the only one done. This order reflects that + -- hardware behavior. + if VBat_Conversion (This, Conversion.Channel) then + Enable_VBat_Connection; + elsif VRef_TemperatureSensor_Conversion (This, Conversion.Channel) + then + Enable_VRef_TemperatureSensor_Connection; + end if; + end; + end loop; + + This.JSQR.JL := UInt2 (Conversions'Length - 1); -- biased rep + end Configure_Injected_Conversions; + + ---------------------------- + -- Enable_VBat_Connection -- + ---------------------------- + + procedure Enable_VBat_Connection is + begin + ADC_Common_Periph.CCR.VBATE := True; + end Enable_VBat_Connection; + + ------------------ + -- VBat_Enabled -- + ------------------ + + function VBat_Enabled return Boolean is + (ADC_Common_Periph.CCR.VBATE); + + ---------------------------------------------- + -- Enable_VRef_TemperatureSensor_Connection -- + ---------------------------------------------- + + procedure Enable_VRef_TemperatureSensor_Connection is + begin + ADC_Common_Periph.CCR.TSVREFE := True; + delay until Clock + Temperature_Sensor_Stabilization; + end Enable_VRef_TemperatureSensor_Connection; + + -------------------------------------- + -- VRef_TemperatureSensor_Connected -- + -------------------------------------- + + function VRef_TemperatureSensor_Enabled return Boolean is + (ADC_Common_Periph.CCR.TSVREFE); + + ---------------------------------- + -- Regular_Conversions_Expected -- + ---------------------------------- + + function Regular_Conversions_Expected (This : Analog_To_Digital_Converter) + return Natural is + (Natural (This.SQR1.L) + 1); + + ----------------------------------- + -- Injected_Conversions_Expected -- + ----------------------------------- + + function Injected_Conversions_Expected (This : Analog_To_Digital_Converter) + return Natural is + (Natural (This.JSQR.JL) + 1); + + ----------------------- + -- Scan_Mode_Enabled -- + ----------------------- + + function Scan_Mode_Enabled (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR1.SCAN); + + --------------------------- + -- EOC_Selection_Enabled -- + --------------------------- + + function EOC_Selection_Enabled (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR2.EOCS); + + ------------------------------- + -- Configure_Regular_Channel -- + ------------------------------- + + procedure Configure_Regular_Channel + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Regular_Channel_Rank; + Sample_Time : Channel_Sampling_Times) + is + begin + Set_Sampling_Time (This, Channel, Sample_Time); + Set_Sequence_Position (This, Channel, Rank); + end Configure_Regular_Channel; + + -------------------------------- + -- Configure_Injected_Channel -- + -------------------------------- + + procedure Configure_Injected_Channel + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Injected_Channel_Rank; + Sample_Time : Channel_Sampling_Times; + Offset : Injected_Data_Offset) + is + begin + Set_Sampling_Time (This, Channel, Sample_Time); + Set_Injected_Channel_Sequence_Position (This, Channel, Rank); + Set_Injected_Channel_Offset (This, Rank, Offset); + end Configure_Injected_Channel; + + ---------------------- + -- Start_Conversion -- + ---------------------- + + procedure Start_Conversion (This : in out Analog_To_Digital_Converter) is + begin + if External_Trigger'Val (This.CR2.EXTEN) /= Trigger_Disabled then + return; + end if; + + if This'Address = STM32_SVD.ADC1_Base + then + This.CR2.SWSTART := True; + end if; + end Start_Conversion; + + ------------------------ + -- Conversion_Started -- + ------------------------ + + function Conversion_Started (This : Analog_To_Digital_Converter) + return Boolean + is + (This.CR2.SWSTART); + + ------------------------------- + -- Start_Injected_Conversion -- + ------------------------------- + + procedure Start_Injected_Conversion + (This : in out Analog_To_Digital_Converter) + is + begin + This.CR2.JSWSTART := True; + end Start_Injected_Conversion; + + --------------------------------- + -- Injected_Conversion_Started -- + --------------------------------- + + function Injected_Conversion_Started (This : Analog_To_Digital_Converter) + return Boolean + is + (This.CR2.JSWSTART); + + ------------------------------ + -- Watchdog_Enable_Channels -- + ------------------------------ + + procedure Watchdog_Enable_Channels + (This : in out Analog_To_Digital_Converter; + Mode : Multiple_Channels_Watchdog; + Low : Watchdog_Threshold; + High : Watchdog_Threshold) + is + begin + This.HTR.HT := High; + This.LTR.LT := Low; + -- see RM 13.3.7, pg 391, table 66 + case Mode is + when Watchdog_All_Regular_Channels => + This.CR1.AWDEN := True; + when Watchdog_All_Injected_Channels => + This.CR1.JAWDEN := True; + when Watchdog_All_Both_Kinds => + This.CR1.AWDEN := True; + This.CR1.JAWDEN := True; + end case; + end Watchdog_Enable_Channels; + + ----------------------------- + -- Watchdog_Enable_Channel -- + ----------------------------- + + procedure Watchdog_Enable_Channel + (This : in out Analog_To_Digital_Converter; + Mode : Single_Channel_Watchdog; + Channel : Analog_Input_Channel; + Low : Watchdog_Threshold; + High : Watchdog_Threshold) + is + begin + This.HTR.HT := High; + This.LTR.LT := Low; + + -- Set then channel + This.CR1.AWDCH := Channel; + -- Enable single channel mode + This.CR1.AWDSGL := True; + + case Mode is + when Watchdog_Single_Regular_Channel => + This.CR1.AWDEN := True; + when Watchdog_Single_Injected_Channel => + This.CR1.JAWDEN := True; + when Watchdog_Single_Both_Kinds => + This.CR1.AWDEN := True; + This.CR1.JAWDEN := True; + end case; + end Watchdog_Enable_Channel; + + ---------------------- + -- Watchdog_Disable -- + ---------------------- + + procedure Watchdog_Disable (This : in out Analog_To_Digital_Converter) is + begin + This.CR1.AWDEN := False; + This.CR1.JAWDEN := False; + + -- clearing the single-channel bit (AWGSDL) is not required to disable, + -- per the RM table 66, section 13.3.7, pg 391, but seems cleanest + This.CR1.AWDSGL := False; + end Watchdog_Disable; + + ---------------------- + -- Watchdog_Enabled -- + ---------------------- + + function Watchdog_Enabled (This : Analog_To_Digital_Converter) + return Boolean + is + (This.CR1.AWDEN or This.CR1.JAWDEN); + -- per the RM table 66, section 13.3.7, pg 391 + + ------------------------------- + -- Enable_Discontinuous_Mode -- + ------------------------------- + + procedure Enable_Discontinuous_Mode + (This : in out Analog_To_Digital_Converter; + Regular : Boolean; -- if False, enabling for Injected channels + Count : Discontinuous_Mode_Channel_Count) + is + begin + if Regular then + This.CR1.JDISCEN := False; + This.CR1.DISCEN := True; + else -- Injected + This.CR1.DISCEN := False; + This.CR1.JDISCEN := True; + end if; + This.CR1.DISCNUM := UInt3 (Count - 1); -- biased + end Enable_Discontinuous_Mode; + + ---------------------------------------- + -- Disable_Discontinuous_Mode_Regular -- + --------------------------------------- + + procedure Disable_Discontinuous_Mode_Regular + (This : in out Analog_To_Digital_Converter) + is + begin + This.CR1.DISCEN := False; + end Disable_Discontinuous_Mode_Regular; + + ----------------------------------------- + -- Disable_Discontinuous_Mode_Injected -- + ----------------------------------------- + + procedure Disable_Discontinuous_Mode_Injected + (This : in out Analog_To_Digital_Converter) + is + begin + This.CR1.JDISCEN := False; + end Disable_Discontinuous_Mode_Injected; + + ---------------------------------------- + -- Discontinuous_Mode_Regular_Enabled -- + ---------------------------------------- + + function Discontinuous_Mode_Regular_Enabled + (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR1.DISCEN); + + ----------------------------------------- + -- Discontinuous_Mode_Injected_Enabled -- + ----------------------------------------- + + function Discontinuous_Mode_Injected_Enabled + (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR1.JDISCEN); + + --------------------------- + -- AutoInjection_Enabled -- + --------------------------- + + function AutoInjection_Enabled + (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR1.JAUTO); + + ---------------- + -- Enable_DMA -- + ---------------- + + procedure Enable_DMA (This : in out Analog_To_Digital_Converter) is + begin + This.CR2.DMA := True; + end Enable_DMA; + + ----------------- + -- Disable_DMA -- + ----------------- + + procedure Disable_DMA (This : in out Analog_To_Digital_Converter) is + begin + This.CR2.DMA := False; + end Disable_DMA; + + ----------------- + -- DMA_Enabled -- + ----------------- + + function DMA_Enabled (This : Analog_To_Digital_Converter) return Boolean is + (This.CR2.DMA); + + ------------------------------------ + -- Enable_DMA_After_Last_Transfer -- + ------------------------------------ + + procedure Enable_DMA_After_Last_Transfer + (This : in out Analog_To_Digital_Converter) + is + begin + This.CR2.DDS := True; + end Enable_DMA_After_Last_Transfer; + + ------------------------------------- + -- Disable_DMA_After_Last_Transfer -- + ------------------------------------- + + procedure Disable_DMA_After_Last_Transfer + (This : in out Analog_To_Digital_Converter) + is + begin + This.CR2.DDS := False; + end Disable_DMA_After_Last_Transfer; + + ------------------------------------- + -- DMA_Enabled_After_Last_Transfer -- + ------------------------------------- + + function DMA_Enabled_After_Last_Transfer + (This : Analog_To_Digital_Converter) + return Boolean + is (This.CR2.DDS); + + ------------------------------------------ + -- Multi_Enable_DMA_After_Last_Transfer -- + ------------------------------------------ + + procedure Multi_Enable_DMA_After_Last_Transfer is + begin + ADC_Common_Periph.CCR.DMA := 1; + end Multi_Enable_DMA_After_Last_Transfer; + + ------------------------------------------- + -- Multi_Disable_DMA_After_Last_Transfer -- + ------------------------------------------- + + procedure Multi_Disable_DMA_After_Last_Transfer is + begin + ADC_Common_Periph.CCR.DMA := 0; + end Multi_Disable_DMA_After_Last_Transfer; + + ------------------------------------------- + -- Multi_DMA_Enabled_After_Last_Transfer -- + ------------------------------------------- + + function Multi_DMA_Enabled_After_Last_Transfer return Boolean is + (ADC_Common_Periph.CCR.DMA = 1); + + --------------------- + -- Poll_For_Status -- + --------------------- + + procedure Poll_For_Status + (This : in out Analog_To_Digital_Converter; + Flag : ADC_Status_Flag; + Success : out Boolean; + Timeout : Time_Span := Time_Span_Last) + is + Deadline : constant Time := Clock + Timeout; + begin + Success := False; + while Clock < Deadline loop + if Status (This, Flag) then + Success := True; + exit; + end if; + end loop; + end Poll_For_Status; + + ------------ + -- Status -- + ------------ + + function Status + (This : Analog_To_Digital_Converter; + Flag : ADC_Status_Flag) + return Boolean + is + begin + case Flag is + when Overrun => + return This.SR.OVR; + when Regular_Channel_Conversion_Started => + return This.SR.STRT; + when Injected_Channel_Conversion_Started => + return This.SR.JSTRT; + when Injected_Channel_Conversion_Complete => + return This.SR.JEOC; + when Regular_Channel_Conversion_Complete => + return This.SR.EOC; + when Analog_Watchdog_Event_Occurred => + return This.SR.AWD; + end case; + end Status; + + ------------------ + -- Clear_Status -- + ------------------ + + procedure Clear_Status + (This : in out Analog_To_Digital_Converter; + Flag : ADC_Status_Flag) + is + begin + case Flag is + when Overrun => + This.SR.OVR := False; + when Regular_Channel_Conversion_Started => + This.SR.STRT := False; + when Injected_Channel_Conversion_Started => + This.SR.JSTRT := False; + when Injected_Channel_Conversion_Complete => + This.SR.JEOC := False; + when Regular_Channel_Conversion_Complete => + This.SR.EOC := False; + when Analog_Watchdog_Event_Occurred => + This.SR.AWD := False; + end case; + end Clear_Status; + + ----------------------- + -- Enable_Interrupts -- + ----------------------- + + procedure Enable_Interrupts + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + is + begin + case Source is + when Overrun => + This.CR1.OVRIE := True; + when Injected_Channel_Conversion_Complete => + This.CR1.JEOCIE := True; + when Regular_Channel_Conversion_Complete => + This.CR1.EOCIE := True; + when Analog_Watchdog_Event => + This.CR1.AWDIE := True; + end case; + end Enable_Interrupts; + + ----------------------- + -- Interrupt_Enabled -- + ----------------------- + + function Interrupt_Enabled + (This : Analog_To_Digital_Converter; + Source : ADC_Interrupts) + return Boolean + is + begin + case Source is + when Overrun => + return This.CR1.OVRIE; + when Injected_Channel_Conversion_Complete => + return This.CR1.JEOCIE; + when Regular_Channel_Conversion_Complete => + return This.CR1.EOCIE; + when Analog_Watchdog_Event => + return This.CR1.AWDIE; + end case; + end Interrupt_Enabled; + + ------------------------ + -- Disable_Interrupts -- + ------------------------ + + procedure Disable_Interrupts + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + is + begin + case Source is + when Overrun => + This.CR1.OVRIE := False; + when Injected_Channel_Conversion_Complete => + This.CR1.JEOCIE := False; + when Regular_Channel_Conversion_Complete => + This.CR1.EOCIE := False; + when Analog_Watchdog_Event => + This.CR1.AWDIE := False; + end case; + end Disable_Interrupts; + + ----------------------------- + -- Clear_Interrupt_Pending -- + ----------------------------- + + procedure Clear_Interrupt_Pending + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + is + begin + case Source is + when Overrun => + This.SR.OVR := False; + when Injected_Channel_Conversion_Complete => + This.SR.JEOC := False; + when Regular_Channel_Conversion_Complete => + This.SR.EOC := False; + when Analog_Watchdog_Event => + This.SR.AWD := False; + end case; + end Clear_Interrupt_Pending; + + --------------------------- + -- Set_Sequence_Position -- + --------------------------- + + procedure Set_Sequence_Position + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Regular_Channel_Rank) + is + begin + case Rank is + when 1 .. 6 => + This.SQR3.SQ.Arr (Integer (Rank)) := Channel; + when 7 .. 12 => + This.SQR2.SQ.Arr (Integer (Rank)) := Channel; + when 13 .. 16 => + This.SQR1.SQ.Arr (Integer (Rank)) := Channel; + end case; + end Set_Sequence_Position; + + -------------------------------------------- + -- Set_Injected_Channel_Sequence_Position -- + -------------------------------------------- + + procedure Set_Injected_Channel_Sequence_Position + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Injected_Channel_Rank) + is + begin + This.JSQR.JSQ.Arr (Integer (Rank)) := Channel; + end Set_Injected_Channel_Sequence_Position; + + ----------------------- + -- Set_Sampling_Time -- + ----------------------- + + procedure Set_Sampling_Time + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Sample_Time : Channel_Sampling_Times) + is + begin +-- if Channel > 9 then +-- This.SMPR1.SMP.Arr (Natural (Channel)) := +-- Channel_Sampling_Times'Enum_Rep (Sample_Time); +-- else +-- This.SMPR2.SMP.Arr (Natural (Channel)) := +-- Channel_Sampling_Times'Enum_Rep (Sample_Time); +-- end if; + null; + end Set_Sampling_Time; + + --------------------------------- + -- Set_Injected_Channel_Offset -- + --------------------------------- + + procedure Set_Injected_Channel_Offset + (This : in out Analog_To_Digital_Converter; + Rank : Injected_Channel_Rank; + Offset : Injected_Data_Offset) + is + begin + case Rank is + when 1 => This.JOFR1.JOFFSET1 := Offset; + when 2 => This.JOFR2.JOFFSET2 := Offset; + when 3 => This.JOFR3.JOFFSET3 := Offset; + when 4 => This.JOFR4.JOFFSET4 := Offset; + end case; + end Set_Injected_Channel_Offset; + +end STM32.ADC; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-adc.ads b/arch/ARM/STM32/devices/stm32f401/stm32-adc.ads new file mode 100644 index 000000000..d1c952294 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-adc.ads @@ -0,0 +1,747 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2017, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_adc.h -- +-- @author MCD Application Team -- +-- @version V1.3.1 -- +-- @date 25-March-2015 -- +-- @brief Header file of ADC HAL module. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides interfaces for the analog-to-digital converters on the +-- STM32F4 (ARM Cortex M4F) microcontrollers from ST Microelectronics. + +-- Channels are mapped to GPIO_Point values as follows. See +-- the STM32F40x datasheet, Table 7. "STM32F40x pin and ball definitions" +-- +-- Channel ADC ADC ADC +-- # 1 2 3 +-- +-- 0 PA0 PA0 PA0 +-- 1 PA1 PA1 PA1 +-- 2 PA2 PA2 PA2 +-- 3 PA3 PA3 PA3 +-- 4 PA4 PA4 PF6 +-- 5 PA5 PA5 PF7 +-- 6 PA6 PA6 PF8 +-- 7 PA7 PA7 PF9 +-- 8 PB0 PB0 PF10 +-- 9 PB1 PB1 PF3 +-- 10 PC0 PC0 PC0 +-- 11 PC1 PC1 PC1 +-- 12 PC2 PC2 PC2 +-- 13 PC3 PC3 PC3 +-- 14 PC4 PC4 PF4 +-- 15 PC5 PC5 PF5 + +with System; use System; +with Ada.Real_Time; use Ada.Real_Time; + +private with STM32_SVD.ADC; + +package STM32.ADC is + pragma Elaborate_Body; + + type Analog_To_Digital_Converter is limited private; + + subtype Analog_Input_Channel is UInt5 range 0 .. 18; + + type ADC_Point is record + ADC : access Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + end record; + + VRef_Channel : constant Analog_Input_Channel := 17; + -- See RM pg 389 section 13.3.3 + -- Note only available with ADC_1 + + VBat_Channel : constant Analog_Input_Channel := 18; + -- See RM pg 410, section 13.10; also pg 389 section 13.3.3 + -- Note only available with ADC_1 + + subtype TemperatureSensor_Channel is Analog_Input_Channel; + -- TODO: ??? The below predicate does not compile with GNAT GPL 2015. + -- with Static_Predicate => TemperatureSensor_Channel in 16 | VBat_Channel; + -- See RM pg 389 section 13.3.3. On some MCUs the temperature channel is + -- the same as the VBat channel, on others it is channel 16. Note only + -- available with ADC_1 + + ADC_Supply_Voltage : constant := 3000; -- millivolts + -- This is the ideal value, likely not the actual + + procedure Enable (This : in out Analog_To_Digital_Converter) with + Post => Enabled (This); + + procedure Disable (This : in out Analog_To_Digital_Converter) with + Post => not Enabled (This); + + function Enabled (This : Analog_To_Digital_Converter) return Boolean; + + type ADC_Resolution is + (ADC_Resolution_12_Bits, -- 15 ADC Clock cycles + ADC_Resolution_10_Bits, -- 13 ADC Clock cycles + ADC_Resolution_8_Bits, -- 11 ADC Clock cycles + ADC_Resolution_6_Bits); -- 9 ADC Clock cycles + + type Data_Alignment is (Right_Aligned, Left_Aligned); + + procedure Configure_Unit + (This : in out Analog_To_Digital_Converter; + Resolution : ADC_Resolution; + Alignment : Data_Alignment) + with + Post => Current_Resolution (This) = Resolution and + Current_Alignment (This) = Alignment; + + function Current_Resolution (This : Analog_To_Digital_Converter) + return ADC_Resolution; + + function Current_Alignment (This : Analog_To_Digital_Converter) + return Data_Alignment; + + type Channel_Sampling_Times is + (Sample_3_Cycles, + Sample_15_Cycles, + Sample_28_Cycles, + Sample_56_Cycles, + Sample_84_Cycles, + Sample_112_Cycles, + Sample_144_Cycles, + Sample_480_Cycles) + with Size => 3; + + type External_Trigger is + (Trigger_Disabled, + Trigger_Rising_Edge, + Trigger_Falling_Edge, + Trigger_Both_Edges); + + type Regular_Channel_Rank is new Natural range 1 .. 16; + + type Injected_Channel_Rank is new Natural range 1 .. 4; + + type External_Events_Regular_Group is + (Timer1_CC1_Event, + Timer1_CC2_Event, + Timer1_CC3_Event, + Timer2_CC2_Event, + Timer2_CC3_Event, + Timer2_CC4_Event, + Timer2_TRGO_Event, + Timer3_CC1_Event, + Timer3_TRGO_Event, + Timer4_CC4_Event, + Timer5_CC1_Event, + Timer5_CC2_Event, + Timer5_CC3_Event, + Timer8_CC1_Event, + Timer8_TRGO_Event, + EXTI_Line11); + + type Regular_Channel_Conversion_Trigger (Enabler : External_Trigger) is + record + case Enabler is + when Trigger_Disabled => + null; + when others => + Event : External_Events_Regular_Group; + end case; + end record; + + Software_Triggered : constant Regular_Channel_Conversion_Trigger + := (Enabler => Trigger_Disabled); + + type Regular_Channel_Conversion is record + Channel : Analog_Input_Channel; + Sample_Time : Channel_Sampling_Times; + end record; + + type Regular_Channel_Conversions is + array (Regular_Channel_Rank range <>) of Regular_Channel_Conversion; + + procedure Configure_Regular_Conversions + (This : in out Analog_To_Digital_Converter; + Continuous : Boolean; + Trigger : Regular_Channel_Conversion_Trigger; + Enable_EOC : Boolean; + Conversions : Regular_Channel_Conversions) + with + Pre => Conversions'Length > 0, + Post => + Length_Matches_Expected (This, Conversions) and + -- if there are multiple channels to be converted, we must want to + -- scan them so we set Scan_Mode accordingly + (if Conversions'Length > 1 then Scan_Mode_Enabled (This)) and + (if Enable_EOC then EOC_Selection_Enabled (This)) and + -- The VBat and VRef internal connections are enabled if This is + -- ADC_1 and the corresponding channels are included in the lists. + (VBat_May_Be_Enabled (This, Conversions) or else + VRef_TemperatureSensor_May_Be_Enabled (This, Conversions)); + -- Configures all the regular channel conversions described in the array + -- Conversions. Note that the order of conversions in the array is the + -- order in which they are scanned, ie, their index is their "rank" in + -- the data structure. Note that if the VBat and Temperature channels are + -- the same channel, then only the VBat conversion takes place and only + -- that one will be enabled, so we must check the two in that order. + + function Regular_Conversions_Expected (This : Analog_To_Digital_Converter) + return Natural; + -- Returns the total number of regular channel conversions specified in the + -- hardware + + function Scan_Mode_Enabled (This : Analog_To_Digital_Converter) + return Boolean; + -- Returns whether only one channel is converted, or if multiple channels + -- are converted (i.e., scanned). Note that this is independent of whether + -- the conversions are continuous. + + function EOC_Selection_Enabled (This : Analog_To_Digital_Converter) + return Boolean; + -- Returns whether the End of Conversion Selection (EOCS) bit is enabled. + -- See the EOCS bit definition, RM pg 417. + -- + -- When EOCS is not enabled, the EOC bit in the Status Register is set at + -- the end of each *sequence* of regular conversions. Overrun detection is + -- enabled only if DMA is enabled. + -- + -- When EOCS is enabled, the EOC bit in the SR is set at the end of each + -- *individual* regular conversion, and overrun detection is enabled. + + type External_Events_Injected_Group is + (Timer1_CC4_Event, + Timer1_TRGO_Event, + Timer2_CC1_Event, + Timer2_TRGO_Event, + Timer3_CC2_Event, + Timer3_CC4_Event, + Timer4_CC1_Event, + Timer4_CC2_Event, + Timer4_CC3_Event, + Timer4_TRGO_Event, + Timer5_CC4_Event, + Timer5_TRGO_Event, + Timer8_CC2_Event, + Timer8_CC3_Event, + Timer8_CC4_Event, + EXTI_Line15); + + type Injected_Channel_Conversion_Trigger (Enabler : External_Trigger) is + record + case Enabler is + when Trigger_Disabled => + null; + when others => + Event : External_Events_Injected_Group; + end case; + end record; + + Software_Triggered_Injected : constant Injected_Channel_Conversion_Trigger + := (Enabler => Trigger_Disabled); + + subtype Injected_Data_Offset is UInt12; + + type Injected_Channel_Conversion is record + Channel : Analog_Input_Channel; + Sample_Time : Channel_Sampling_Times; + Offset : Injected_Data_Offset := 0; + end record; + + type Injected_Channel_Conversions is + array (Injected_Channel_Rank range <>) of Injected_Channel_Conversion; + + procedure Configure_Injected_Conversions + (This : in out Analog_To_Digital_Converter; + AutoInjection : Boolean; + Trigger : Injected_Channel_Conversion_Trigger; + Enable_EOC : Boolean; + Conversions : Injected_Channel_Conversions) + with + Pre => + Conversions'Length > 0 and + (if AutoInjection then Trigger = Software_Triggered_Injected) and + (if AutoInjection then + not Discontinuous_Mode_Injected_Enabled (This)), + Post => + Length_Is_Expected (This, Conversions) and + (if Enable_EOC then EOC_Selection_Enabled (This)) and + -- The VBat and VRef internal connections are enabled if This is + -- ADC_1 and the corresponding channels are included in the lists. + (VBat_May_Be_Enabled (This, Conversions) or else + VRef_TemperatureSensor_May_Be_Enabled (This, Conversions)); + -- Configures all the injected channel conversions described in the array + -- Conversions. Note that the order of conversions in the array is the + -- order in which they are scanned, ie, their index is their "rank" in + -- the data structure. Note that if the VBat and Temperature channels are + -- the same channel, then only the VBat conversion takes place and only + -- that one will be enabled, so we must check the two in that order. + + function Injected_Conversions_Expected (This : Analog_To_Digital_Converter) + return Natural; + -- Returns the total number of injected channel conversions to be done + + function VBat_Enabled return Boolean; + -- Returns whether the hardware has the VBat internal connection enabled + + function VRef_TemperatureSensor_Enabled return Boolean; + -- Returns whether the hardware has the VRef or temperature sensor internal + -- connection enabled + + procedure Start_Conversion (This : in out Analog_To_Digital_Converter) with + Pre => Enabled (This) and Regular_Conversions_Expected (This) > 0; + -- Starts the conversion(s) for the regular channels + + function Conversion_Started (This : Analog_To_Digital_Converter) + return Boolean; + -- Returns whether the regular channels' conversions have started. Note + -- that the ADC hardware clears the corresponding bit immediately, as + -- part of starting. + + function Conversion_Value (This : Analog_To_Digital_Converter) + return UInt16 with Inline; + -- Returns the latest regular conversion result for the specified ADC unit + + function Data_Register_Address (This : Analog_To_Digital_Converter) + return System.Address + with Inline; + -- Returns the address of the ADC Data Register. This is exported + -- STRICTLY for the sake of clients using DMA. All other + -- clients of this package should use the Conversion_Value functions! + -- Seriously, don't use this function otherwise. + + procedure Start_Injected_Conversion + (This : in out Analog_To_Digital_Converter) + with Pre => Enabled (This) and Injected_Conversions_Expected (This) > 0; + -- Note that the ADC hardware clears the corresponding bit immediately, as + -- part of starting. + + function Injected_Conversion_Started (This : Analog_To_Digital_Converter) + return Boolean; + -- Returns whether the injected channels' conversions have started + + function Injected_Conversion_Value + (This : Analog_To_Digital_Converter; + Rank : Injected_Channel_Rank) + return UInt16 + with Inline; + -- Returns the latest conversion result for the analog input channel at + -- the injected sequence position given by Rank on the specified ADC unit. + -- + -- Note that the offset corresponding to the specified Rank is subtracted + -- automatically, so check the sign bit for a negative result. + + type Discontinuous_Mode_Channel_Count is range 1 .. 8; + -- Note this uses a biased representation implicitly because the underlying + -- representational bit values are 0 ... 7 + + procedure Enable_Discontinuous_Mode + (This : in out Analog_To_Digital_Converter; + Regular : Boolean; -- if False, applies to Injected channels + Count : Discontinuous_Mode_Channel_Count) + with + Pre => not AutoInjection_Enabled (This), + Post => + (if Regular then + (Discontinuous_Mode_Regular_Enabled (This)) and + (not Discontinuous_Mode_Injected_Enabled (This)) + else + (not Discontinuous_Mode_Regular_Enabled (This)) and + (Discontinuous_Mode_Injected_Enabled (This))); + -- Enables discontinuous mode and sets the count. If Regular is True, + -- enables the mode only for regular channels. If Regular is False, enables + -- the mode only for Injected channels. The note in RM 13.3.10, pg 393, + -- says we cannot enable the mode for both regular and injected channels + -- at the same time, so this flag ensures we follow that rule. + + procedure Disable_Discontinuous_Mode_Regular + (This : in out Analog_To_Digital_Converter) + with Post => not Discontinuous_Mode_Regular_Enabled (This); + + procedure Disable_Discontinuous_Mode_Injected + (This : in out Analog_To_Digital_Converter) + with Post => not Discontinuous_Mode_Injected_Enabled (This); + + function Discontinuous_Mode_Regular_Enabled + (This : Analog_To_Digital_Converter) + return Boolean; + + function Discontinuous_Mode_Injected_Enabled + (This : Analog_To_Digital_Converter) + return Boolean; + + function AutoInjection_Enabled + (This : Analog_To_Digital_Converter) + return Boolean; + + -- DMA Management -------------------------------------------------------- + + procedure Enable_DMA (This : in out Analog_To_Digital_Converter) with + Post => DMA_Enabled (This); + + procedure Disable_DMA (This : in out Analog_To_Digital_Converter) with + Post => not DMA_Enabled (This); + + function DMA_Enabled (This : Analog_To_Digital_Converter) return Boolean; + + procedure Enable_DMA_After_Last_Transfer + (This : in out Analog_To_Digital_Converter) with + Post => DMA_Enabled_After_Last_Transfer (This); + + procedure Disable_DMA_After_Last_Transfer + (This : in out Analog_To_Digital_Converter) with + Post => not DMA_Enabled_After_Last_Transfer (This); + + function DMA_Enabled_After_Last_Transfer + (This : Analog_To_Digital_Converter) + return Boolean; + + -- Analog Watchdog ------------------------------------------------------- + + subtype Watchdog_Threshold is UInt12; + + type Analog_Watchdog_Modes is + (Watchdog_All_Regular_Channels, + Watchdog_All_Injected_Channels, + Watchdog_All_Both_Kinds, + Watchdog_Single_Regular_Channel, + Watchdog_Single_Injected_Channel, + Watchdog_Single_Both_Kinds); + + subtype Multiple_Channels_Watchdog is Analog_Watchdog_Modes + range Watchdog_All_Regular_Channels .. Watchdog_All_Both_Kinds; + + procedure Watchdog_Enable_Channels + (This : in out Analog_To_Digital_Converter; + Mode : Multiple_Channels_Watchdog; + Low : Watchdog_Threshold; + High : Watchdog_Threshold) + with + Pre => not Watchdog_Enabled (This), + Post => Watchdog_Enabled (This); + -- Enables the watchdog on all channels; channel kind depends on Mode. + -- A call to this routine is considered a complete configuration of the + -- watchdog so do not call the other enabler routine (for a single channel) + -- while this configuration is active. You must first disable the watchdog + -- if you want to enable the watchdog for a single channel. + + subtype Single_Channel_Watchdog is Analog_Watchdog_Modes + range Watchdog_Single_Regular_Channel .. Watchdog_Single_Both_Kinds; + + procedure Watchdog_Enable_Channel + (This : in out Analog_To_Digital_Converter; + Mode : Single_Channel_Watchdog; + Channel : Analog_Input_Channel; + Low : Watchdog_Threshold; + High : Watchdog_Threshold) + with + Pre => not Watchdog_Enabled (This), + Post => Watchdog_Enabled (This); + -- Enables the watchdog on this single channel, and no others. The kind of + -- channel depends on Mode. A call to this routine is considered a complete + -- configuration of the watchdog so do not call the other enabler routine + -- (for all channels) while this configuration is active. You must + -- first disable the watchdog if you want to enable the watchdog for + -- all channels. + + procedure Watchdog_Disable (This : in out Analog_To_Digital_Converter) + with Post => not Watchdog_Enabled (This); + -- Whether watching a single channel or all of them, the watchdog is now + -- disabled + + function Watchdog_Enabled (This : Analog_To_Digital_Converter) + return Boolean; + + -- Status Management ----------------------------------------------------- + + type ADC_Status_Flag is + (Overrun, + Regular_Channel_Conversion_Started, + Injected_Channel_Conversion_Started, + Injected_Channel_Conversion_Complete, + Regular_Channel_Conversion_Complete, + Analog_Watchdog_Event_Occurred); + + function Status + (This : Analog_To_Digital_Converter; + Flag : ADC_Status_Flag) + return Boolean + with Inline; + -- Returns whether Flag is indicated, ie set in the Status Register + + procedure Clear_Status + (This : in out Analog_To_Digital_Converter; + Flag : ADC_Status_Flag) + with + Inline, + Post => not Status (This, Flag); + + procedure Poll_For_Status + (This : in out Analog_To_Digital_Converter; + Flag : ADC_Status_Flag; + Success : out Boolean; + Timeout : Time_Span := Time_Span_Last); + -- Continuously polls for the specified status flag to be set, up to the + -- deadline computed by the value of Clock + Timeout. Sets the Success + -- argument accordingly. The default Time_Span_Last value is the largest + -- possible value, thereby setting a very long, but not infinite, timeout. + + -- Interrupt Management -------------------------------------------------- + + type ADC_Interrupts is + (Overrun, + Injected_Channel_Conversion_Complete, + Regular_Channel_Conversion_Complete, + Analog_Watchdog_Event); + + procedure Enable_Interrupts + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + with + Inline, + Post => Interrupt_Enabled (This, Source); + + procedure Disable_Interrupts + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + with + Inline, + Post => not Interrupt_Enabled (This, Source); + + function Interrupt_Enabled + (This : Analog_To_Digital_Converter; + Source : ADC_Interrupts) + return Boolean + with Inline; + + procedure Clear_Interrupt_Pending + (This : in out Analog_To_Digital_Converter; + Source : ADC_Interrupts) + with Inline; + + -- Common Properties ------------------------------------------------------ + + type ADC_Prescalars is + (PCLK2_Div_2, + PCLK2_Div_4, + PCLK2_Div_6, + PCLK2_Div_8); + + type Multi_ADC_DMA_Modes is + (Disabled, + DMA_Mode_1, + DMA_Mode_2, + DMA_Mode_3); + + type Sampling_Delay_Selections is + (Sampling_Delay_5_Cycles, + Sampling_Delay_6_Cycles, + Sampling_Delay_7_Cycles, + Sampling_Delay_8_Cycles, + Sampling_Delay_9_Cycles, + Sampling_Delay_10_Cycles, + Sampling_Delay_11_Cycles, + Sampling_Delay_12_Cycles, + Sampling_Delay_13_Cycles, + Sampling_Delay_14_Cycles, + Sampling_Delay_15_Cycles, + Sampling_Delay_16_Cycles, + Sampling_Delay_17_Cycles, + Sampling_Delay_18_Cycles, + Sampling_Delay_19_Cycles, + Sampling_Delay_20_Cycles); + + type Multi_ADC_Mode_Selections is + (Independent, + Dual_Combined_Regular_Injected_Simultaneous, + Dual_Combined_Regular_Simultaneous_Alternate_Trigger, + Dual_Injected_Simultaneous, + Dual_Regular_Simultaneous, + Dual_Interleaved, + Dual_Alternate_Trigger, + Triple_Combined_Regular_Injected_Simultaneous, + Triple_Combined_Regular_Simultaneous_Alternate_Trigger, + Triple_Injected_Simultaneous, + Triple_Regular_Simultaneous, + Triple_Interleaved, + Triple_Alternate_Trigger); + + for Multi_ADC_Mode_Selections use + (Independent => 2#00000#, + Dual_Combined_Regular_Injected_Simultaneous => 2#00001#, + Dual_Combined_Regular_Simultaneous_Alternate_Trigger => 2#00010#, + Dual_Injected_Simultaneous => 2#00101#, + Dual_Regular_Simultaneous => 2#00110#, + Dual_Interleaved => 2#00111#, + Dual_Alternate_Trigger => 2#01001#, + Triple_Combined_Regular_Injected_Simultaneous => 2#10001#, + Triple_Combined_Regular_Simultaneous_Alternate_Trigger => 2#10010#, + Triple_Injected_Simultaneous => 2#10101#, + Triple_Regular_Simultaneous => 2#10110#, + Triple_Interleaved => 2#10111#, + Triple_Alternate_Trigger => 2#11001#); + + procedure Configure_Common_Properties + (Mode : Multi_ADC_Mode_Selections; + Prescalar : ADC_Prescalars; + DMA_Mode : Multi_ADC_DMA_Modes; + Sampling_Delay : Sampling_Delay_Selections); + -- These properties are common to all the ADC units on the board. + + -- These Multi_DMA_Mode commands needs to be separate from the + -- Configure_Common_Properties procedure for the sake of dealing + -- with overruns etc. + + procedure Multi_Enable_DMA_After_Last_Transfer with + Post => Multi_DMA_Enabled_After_Last_Transfer; + + procedure Multi_Disable_DMA_After_Last_Transfer with + Post => not Multi_DMA_Enabled_After_Last_Transfer; + + function Multi_DMA_Enabled_After_Last_Transfer return Boolean; + + -- Queries ---------------------------------------------------------------- + + function VBat_Conversion + (This : Analog_To_Digital_Converter; + Channel : Analog_Input_Channel) + return Boolean with Inline; + + function VRef_TemperatureSensor_Conversion + (This : Analog_To_Digital_Converter; + Channel : Analog_Input_Channel) + return Boolean with Inline; + -- Returns whether the ADC unit and channel specified are that of a VRef + -- OR a temperature sensor conversion. Note that one control bit is used + -- to enable either one, ie it is shared. + + function VBat_May_Be_Enabled + (This : Analog_To_Digital_Converter; + These : Regular_Channel_Conversions) + return Boolean + is + ((for all Conversion of These => + (if VBat_Conversion (This, Conversion.Channel) then VBat_Enabled))); + + function VBat_May_Be_Enabled + (This : Analog_To_Digital_Converter; + These : Injected_Channel_Conversions) + return Boolean + is + ((for all Conversion of These => + (if VBat_Conversion (This, Conversion.Channel) then VBat_Enabled))); + + function VRef_TemperatureSensor_May_Be_Enabled + (This : Analog_To_Digital_Converter; + These : Regular_Channel_Conversions) + return Boolean + is + (for all Conversion of These => + (if VRef_TemperatureSensor_Conversion (This, Conversion.Channel) then + VRef_TemperatureSensor_Enabled)); + + function VRef_TemperatureSensor_May_Be_Enabled + (This : Analog_To_Digital_Converter; + These : Injected_Channel_Conversions) + return Boolean + is + (for all Conversion of These => + (if VRef_TemperatureSensor_Conversion (This, Conversion.Channel) then + VRef_TemperatureSensor_Enabled)); + + -- The *_Conversions_Expected functions will always return at least the + -- value 1 because the hardware uses a biased representation (in which + -- zero indicates the value one, one indicates the value two, and so on). + -- Therefore, we don't invoke the functions unless we know they will be + -- greater than zero. + + function Length_Matches_Expected + (This : Analog_To_Digital_Converter; + These : Regular_Channel_Conversions) + return Boolean + is + (if These'Length > 0 then + Regular_Conversions_Expected (This) = These'Length); + + function Length_Is_Expected + (This : Analog_To_Digital_Converter; + These : Injected_Channel_Conversions) + return Boolean + is + (if These'Length > 0 then + Injected_Conversions_Expected (This) = These'Length); + +private + + ADC_Stabilization : constant Time_Span := Microseconds (3); + Temperature_Sensor_Stabilization : constant Time_Span := Microseconds (10); + -- The RM, section 13.3.6, says stabilization times are required. These + -- values are specified in the datasheets, eg section 5.3.20, pg 129, + -- and section 5.3.21, pg 134, of the STM32F405/7xx, DocID022152 Rev 4. + + procedure Configure_Regular_Channel + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Regular_Channel_Rank; + Sample_Time : Channel_Sampling_Times); + + procedure Configure_Injected_Channel + (This : in out Analog_To_Digital_Converter; + Channel : Analog_Input_Channel; + Rank : Injected_Channel_Rank; + Sample_Time : Channel_Sampling_Times; + Offset : Injected_Data_Offset); + + procedure Enable_VBat_Connection with + Post => VBat_Enabled; + + procedure Enable_VRef_TemperatureSensor_Connection with + Post => VRef_TemperatureSensor_Enabled; + -- One bit controls both the VRef and the temperature internal connections + + type Analog_To_Digital_Converter is new STM32_SVD.ADC.ADC1_Peripheral; + + function VBat_Conversion + (This : Analog_To_Digital_Converter; + Channel : Analog_Input_Channel) + return Boolean + is (This'Address = STM32_SVD.ADC.ADC1_Periph'Address and + Channel = VBat_Channel); + + function VRef_TemperatureSensor_Conversion + (This : Analog_To_Digital_Converter; + Channel : Analog_Input_Channel) + return Boolean + is (This'Address = STM32_SVD.ADC.ADC1_Periph'Address and + (Channel in VRef_Channel | TemperatureSensor_Channel)); + +end STM32.ADC; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-device.adb b/arch/ARM/STM32/devices/stm32f401/stm32-device.adb new file mode 100644 index 000000000..dbc4d94f5 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-device.adb @@ -0,0 +1,689 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2016, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System; use System; +with ADL_Config; + +with STM32_SVD.RCC; use STM32_SVD.RCC; + +package body STM32.Device is + + HSE_VALUE : constant := ADL_Config.High_Speed_External_Clock; + -- External oscillator in Hz + + HSI_VALUE : constant := 16_000_000; + -- Internal oscillator in Hz + + HPRE_Presc_Table : constant array (UInt4) of UInt32 := + (1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 16, 64, 128, 256, 512); + + PPRE_Presc_Table : constant array (UInt3) of UInt32 := + (1, 1, 1, 1, 2, 4, 8, 16); + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : aliased in out GPIO_Port) is + begin + if This'Address = GPIOA_Base then + RCC_Periph.AHB1ENR.GPIOAEN := True; + elsif This'Address = GPIOB_Base then + RCC_Periph.AHB1ENR.GPIOBEN := True; + elsif This'Address = GPIOC_Base then + RCC_Periph.AHB1ENR.GPIOCEN := True; + elsif This'Address = GPIOD_Base then + RCC_Periph.AHB1ENR.GPIODEN := True; + elsif This'Address = GPIOE_Base then + RCC_Periph.AHB1ENR.GPIOEEN := True; + elsif This'Address = GPIOH_Base then + RCC_Periph.AHB1ENR.GPIOHEN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (Point : GPIO_Point) + is + begin + Enable_Clock (Point.Periph.all); + end Enable_Clock; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (Points : GPIO_Points) + is + begin + for Point of Points loop + Enable_Clock (Point.Periph.all); + end loop; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : aliased in out GPIO_Port) is + begin + if This'Address = GPIOA_Base then + RCC_Periph.AHB1RSTR.GPIOARST := True; + RCC_Periph.AHB1RSTR.GPIOARST := False; + elsif This'Address = GPIOB_Base then + RCC_Periph.AHB1RSTR.GPIOBRST := True; + RCC_Periph.AHB1RSTR.GPIOBRST := False; + elsif This'Address = GPIOC_Base then + RCC_Periph.AHB1RSTR.GPIOCRST := True; + RCC_Periph.AHB1RSTR.GPIOCRST := False; + elsif This'Address = GPIOD_Base then + RCC_Periph.AHB1RSTR.GPIODRST := True; + RCC_Periph.AHB1RSTR.GPIODRST := False; + elsif This'Address = GPIOE_Base then + RCC_Periph.AHB1RSTR.GPIOERST := True; + RCC_Periph.AHB1RSTR.GPIOERST := False; + elsif This'Address = GPIOH_Base then + RCC_Periph.AHB1RSTR.GPIOHRST := True; + RCC_Periph.AHB1RSTR.GPIOHRST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ----------- + -- Reset -- + ----------- + + procedure Reset (Point : GPIO_Point) is + begin + Reset (Point.Periph.all); + end Reset; + + ----------- + -- Reset -- + ----------- + + procedure Reset (Points : GPIO_Points) + is + Do_Reset : Boolean; + begin + for J in Points'Range loop + Do_Reset := True; + for K in Points'First .. J - 1 loop + if Points (K).Periph = Points (J).Periph then + Do_Reset := False; + + exit; + end if; + end loop; + + if Do_Reset then + Reset (Points (J).Periph.all); + end if; + end loop; + end Reset; + + ------------------------------ + -- GPIO_Port_Representation -- + ------------------------------ + + function GPIO_Port_Representation (Port : GPIO_Port) return UInt4 is + begin + -- TODO: rather ugly to have this board-specific range here + if Port'Address = GPIOA_Base then + return 0; + elsif Port'Address = GPIOB_Base then + return 1; + elsif Port'Address = GPIOC_Base then + return 2; + elsif Port'Address = GPIOD_Base then + return 3; + elsif Port'Address = GPIOE_Base then + return 4; + elsif Port'Address = GPIOH_Base then + return 7; + else + raise Program_Error; + end if; + end GPIO_Port_Representation; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : aliased in out Analog_To_Digital_Converter) + is + begin + if This'Address = ADC1_Base then + RCC_Periph.APB2ENR.ADC1EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ------------------------- + -- Reset_All_ADC_Units -- + ------------------------- + + procedure Reset_All_ADC_Units is + begin + RCC_Periph.APB2RSTR.ADCRST := True; + RCC_Periph.APB2RSTR.ADCRST := False; + end Reset_All_ADC_Units; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : aliased in out USART) is + begin + if This.Periph.all'Address = USART1_Base then + RCC_Periph.APB2ENR.USART1EN := True; + elsif This.Periph.all'Address = USART2_Base then + RCC_Periph.APB1ENR.USART2EN := True; + elsif This.Periph.all'Address = USART6_Base then + RCC_Periph.APB2ENR.USART6EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : aliased in out USART) is + begin + if This.Periph.all'Address = USART1_Base then + RCC_Periph.APB2RSTR.USART1RST := True; + RCC_Periph.APB2RSTR.USART1RST := False; + elsif This.Periph.all'Address = USART2_Base then + RCC_Periph.APB1RSTR.UART2RST := True; + RCC_Periph.APB1RSTR.UART2RST := False; + elsif This.Periph.all'Address = USART6_Base then + RCC_Periph.APB2RSTR.USART6RST := True; + RCC_Periph.APB2RSTR.USART6RST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : aliased in out DMA_Controller) is + begin + if This'Address = STM32_SVD.DMA1_Base then + RCC_Periph.AHB1ENR.DMA1EN := True; + elsif This'Address = STM32_SVD.DMA2_Base then + RCC_Periph.AHB1ENR.DMA2EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : aliased in out DMA_Controller) is + begin + if This'Address = STM32_SVD.DMA1_Base then + RCC_Periph.AHB1RSTR.DMA1RST := True; + RCC_Periph.AHB1RSTR.DMA1RST := False; + elsif This'Address = STM32_SVD.DMA2_Base then + RCC_Periph.AHB1RSTR.DMA2RST := True; + RCC_Periph.AHB1RSTR.DMA2RST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ---------------- + -- As_Port_Id -- + ---------------- + + function As_Port_Id (Port : I2C_Port'Class) return I2C_Port_Id is + begin + if Port.Periph.all'Address = I2C1_Base then + return I2C_Id_1; + elsif Port.Periph.all'Address = I2C2_Base then + return I2C_Id_2; + elsif Port.Periph.all'Address = I2C3_Base then + return I2C_Id_3; + else + raise Unknown_Device; + end if; + end As_Port_Id; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : aliased I2C_Port'Class) is + begin + Enable_Clock (As_Port_Id (This)); + end Enable_Clock; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : I2C_Port_Id) is + begin + case This is + when I2C_Id_1 => + RCC_Periph.APB1ENR.I2C1EN := True; + when I2C_Id_2 => + RCC_Periph.APB1ENR.I2C2EN := True; + when I2C_Id_3 => + RCC_Periph.APB1ENR.I2C3EN := True; + end case; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : I2C_Port'Class) is + begin + Reset (As_Port_Id (This)); + end Reset; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : I2C_Port_Id) is + begin + case This is + when I2C_Id_1 => + RCC_Periph.APB1RSTR.I2C1RST := True; + RCC_Periph.APB1RSTR.I2C1RST := False; + when I2C_Id_2 => + RCC_Periph.APB1RSTR.I2C2RST := True; + RCC_Periph.APB1RSTR.I2C2RST := False; + when I2C_Id_3 => + RCC_Periph.APB1RSTR.I2C3RST := True; + RCC_Periph.APB1RSTR.I2C3RST := False; + end case; + end Reset; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : SPI_Port'Class) is + begin + if This.Periph.all'Address = SPI1_Base then + RCC_Periph.APB2ENR.SPI1EN := True; + elsif This.Periph.all'Address = SPI2_Base then + RCC_Periph.APB1ENR.SPI2EN := True; + elsif This.Periph.all'Address = SPI3_Base then + RCC_Periph.APB1ENR.SPI3EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out SPI_Port'Class) is + begin + if This.Periph.all'Address = SPI1_Base then + RCC_Periph.APB2RSTR.SPI1RST := True; + RCC_Periph.APB2RSTR.SPI1RST := False; + elsif This.Periph.all'Address = SPI2_Base then + RCC_Periph.APB1RSTR.SPI2RST := True; + RCC_Periph.APB1RSTR.SPI2RST := False; + elsif This.Periph.all'Address = SPI3_Base then + RCC_Periph.APB1RSTR.SPI3RST := True; + RCC_Periph.APB1RSTR.SPI3RST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : I2S_Port) is + begin + if This.Periph.all'Address = SPI1_Base then + RCC_Periph.APB2ENR.SPI1EN := True; + elsif This.Periph.all'Address = SPI2_Base + or else + This.Periph.all'Address = I2S2ext_Base + then + RCC_Periph.APB1ENR.SPI2EN := True; + elsif This.Periph.all'Address = SPI3_Base + or else + This.Periph.all'Address = I2S3ext_Base + then + RCC_Periph.APB1ENR.SPI3EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out I2S_Port) is + begin + if This.Periph.all'Address = SPI1_Base then + RCC_Periph.APB2RSTR.SPI1RST := True; + RCC_Periph.APB2RSTR.SPI1RST := False; + elsif This.Periph.all'Address = SPI2_Base then + RCC_Periph.APB1RSTR.SPI2RST := True; + RCC_Periph.APB1RSTR.SPI2RST := False; + elsif This.Periph.all'Address = SPI3_Base then + RCC_Periph.APB1RSTR.SPI3RST := True; + RCC_Periph.APB1RSTR.SPI3RST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : in out Timer) is + begin + if This'Address = TIM1_Base then + RCC_Periph.APB2ENR.TIM1EN := True; + elsif This'Address = TIM2_Base then + RCC_Periph.APB1ENR.TIM2EN := True; + elsif This'Address = TIM3_Base then + RCC_Periph.APB1ENR.TIM3EN := True; + elsif This'Address = TIM4_Base then + RCC_Periph.APB1ENR.TIM4EN := True; + elsif This'Address = TIM5_Base then + RCC_Periph.APB1ENR.TIM5EN := True; + elsif This'Address = TIM9_Base then + RCC_Periph.APB2ENR.TIM9EN := True; + elsif This'Address = TIM10_Base then + RCC_Periph.APB2ENR.TIM10EN := True; + elsif This'Address = TIM11_Base then + RCC_Periph.APB2ENR.TIM11EN := True; + else + raise Unknown_Device; + end if; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out Timer) is + begin + if This'Address = TIM1_Base then + RCC_Periph.APB2RSTR.TIM1RST := True; + RCC_Periph.APB2RSTR.TIM1RST := False; + elsif This'Address = TIM2_Base then + RCC_Periph.APB1RSTR.TIM2RST := True; + RCC_Periph.APB1RSTR.TIM2RST := False; + elsif This'Address = TIM3_Base then + RCC_Periph.APB1RSTR.TIM3RST := True; + RCC_Periph.APB1RSTR.TIM3RST := False; + elsif This'Address = TIM4_Base then + RCC_Periph.APB1RSTR.TIM4RST := True; + RCC_Periph.APB1RSTR.TIM4RST := False; + elsif This'Address = TIM5_Base then + RCC_Periph.APB1RSTR.TIM5RST := True; + RCC_Periph.APB1RSTR.TIM5RST := False; + elsif This'Address = TIM9_Base then + RCC_Periph.APB2RSTR.TIM9RST := True; + RCC_Periph.APB2RSTR.TIM9RST := False; + elsif This'Address = TIM10_Base then + RCC_Periph.APB2RSTR.TIM10RST := True; + RCC_Periph.APB2RSTR.TIM10RST := False; + elsif This'Address = TIM11_Base then + RCC_Periph.APB2RSTR.TIM11RST := True; + RCC_Periph.APB2RSTR.TIM11RST := False; + else + raise Unknown_Device; + end if; + end Reset; + + ------------------------------ + -- System_Clock_Frequencies -- + ------------------------------ + + function System_Clock_Frequencies return RCC_System_Clocks + is + Source : constant CFGR_SWS_Field := RCC_Periph.CFGR.SWS; + Result : RCC_System_Clocks; + begin + Result.I2SCLK := 0; + + case Source is + when 0 => + -- HSI as source + Result.SYSCLK := HSI_VALUE; + when 1 => + -- HSE as source + Result.SYSCLK := HSE_VALUE; + when 2 => + -- PLL as source + declare + HSE_Source : constant Boolean := RCC_Periph.PLLCFGR.PLLSRC; + Pllm : constant UInt32 := + UInt32 (RCC_Periph.PLLCFGR.PLLM); + Plln : constant + UInt32 := + UInt32 (RCC_Periph.PLLCFGR.PLLN); + Pllp : constant + UInt32 := + (UInt32 (RCC_Periph.PLLCFGR.PLLP) + 1) * 2; + Pllvco : UInt32; + begin + if not HSE_Source then + Pllvco := HSI_VALUE; + else + Pllvco := HSE_VALUE; + end if; + + Pllvco := Pllvco / Pllm; + + Result.I2SCLK := Pllvco; + + Pllvco := Pllvco * Plln; + + Result.SYSCLK := Pllvco / Pllp; + end; + when others => + Result.SYSCLK := HSI_VALUE; + end case; + + declare + HPRE : constant UInt4 := RCC_Periph.CFGR.HPRE; + PPRE1 : constant UInt3 := RCC_Periph.CFGR.PPRE.Arr (1); + PPRE2 : constant UInt3 := RCC_Periph.CFGR.PPRE.Arr (2); + begin + Result.HCLK := Result.SYSCLK / HPRE_Presc_Table (HPRE); + Result.PCLK1 := Result.HCLK / PPRE_Presc_Table (PPRE1); + Result.PCLK2 := Result.HCLK / PPRE_Presc_Table (PPRE2); + + -- Timer clocks + -- If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) + -- is configured to a division factor of 1, TIMxCLK = PCLKx. + -- Otherwise, the timer clock frequencies are set to twice to the + -- frequency of the APB domain to which the timers are connected : + -- TIMxCLK = 2xPCLKx. + if PPRE_Presc_Table (PPRE1) = 1 then + Result.TIMCLK1 := Result.PCLK1; + else + Result.TIMCLK1 := Result.PCLK1 * 2; + end if; + if PPRE_Presc_Table (PPRE2) = 1 then + Result.TIMCLK2 := Result.PCLK2; + else + Result.TIMCLK2 := Result.PCLK2 * 2; + end if; + end; + + -- I2S Clock -- + + if RCC_Periph.CFGR.I2SSRC then + -- External clock source + Result.I2SCLK := 0; + raise Program_Error with "External I2S clock value is unknown"; + else + -- Pll clock source + declare + Plli2sn : constant UInt32 := + UInt32 (RCC_Periph.PLLI2SCFGR.PLLI2SNx); + Plli2sr : constant UInt32 + := UInt32 (RCC_Periph.PLLI2SCFGR.PLLI2SRx); + begin + Result.I2SCLK := (Result.I2SCLK * Plli2sn) / Plli2sr; + end; + end if; + + return Result; + end System_Clock_Frequencies; + + -------------------- + -- PLLI2S_Enabled -- + -------------------- + + function PLLI2S_Enabled return Boolean is + (RCC_Periph.CR.PLLI2SRDY); + + ------------------------ + -- Set_PLLI2S_Factors -- + ------------------------ + + procedure Set_PLLI2S_Factors (Pll_N : UInt9; + Pll_R : UInt3) + + is + begin + RCC_Periph.PLLI2SCFGR.PLLI2SNx := Pll_N; + RCC_Periph.PLLI2SCFGR.PLLI2SRx := Pll_R; + end Set_PLLI2S_Factors; + + ------------------- + -- Enable_PLLI2S -- + ------------------- + + procedure Enable_PLLI2S is + begin + RCC_Periph.CR.PLLI2SON := True; + loop + exit when PLLI2S_Enabled; + end loop; + end Enable_PLLI2S; + + -------------------- + -- Disable_PLLI2S -- + -------------------- + + procedure Disable_PLLI2S is + begin + RCC_Periph.CR.PLLI2SON := False; + loop + exit when not PLLI2S_Enabled; + end loop; + end Disable_PLLI2S; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : in out SDMMC_Controller) + is + begin + if This.Periph.all'Address /= SDIO_Base then + raise Unknown_Device; + end if; + + RCC_Periph.APB2ENR.SDIOEN := True; + end Enable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out SDMMC_Controller) + is + begin + if This.Periph.all'Address /= SDIO_Base then + raise Unknown_Device; + end if; + + RCC_Periph.APB2RSTR.SDIORST := True; + RCC_Periph.APB2RSTR.SDIORST := False; + end Reset; + + ------------------ + -- Enable_Clock -- + ------------------ + + procedure Enable_Clock (This : in out CRC_32) is + pragma Unreferenced (This); + begin + RCC_Periph.AHB1ENR.CRCEN := True; + end Enable_Clock; + + ------------------- + -- Disable_Clock -- + ------------------- + + procedure Disable_Clock (This : in out CRC_32) is + pragma Unreferenced (This); + begin + RCC_Periph.AHB1ENR.CRCEN := False; + end Disable_Clock; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out CRC_32) is + pragma Unreferenced (This); + begin + RCC_Periph.AHB1RSTR.CRCRST := True; + RCC_Periph.AHB1RSTR.CRCRST := False; + end Reset; + +end STM32.Device; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-device.ads b/arch/ARM/STM32/devices/stm32f401/stm32-device.ads new file mode 100644 index 000000000..47d6430a3 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-device.ads @@ -0,0 +1,434 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2018, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f40[5|7]xx.h -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides declarations for devices on the STM32F40xxx MCUs +-- manufactured by ST Microelectronics. For example, an STM32F405. + +with STM32_SVD; use STM32_SVD; +with STM32_SVD.SDIO; + +with STM32.DMA; use STM32.DMA; +with STM32.GPIO; use STM32.GPIO; +with STM32.ADC; use STM32.ADC; +with STM32.USARTs; use STM32.USARTs; +with STM32.SPI; use STM32.SPI; +with STM32.SPI.DMA; use STM32.SPI.DMA; +with STM32.I2S; use STM32.I2S; +with STM32.Timers; use STM32.Timers; +with STM32.I2C; use STM32.I2C; +with STM32.I2C.DMA; use STM32.I2C.DMA; +with STM32.RTC; use STM32.RTC; +with STM32.CRC; use STM32.CRC; +with STM32.SDMMC; use STM32.SDMMC; + +package STM32.Device is + pragma Elaborate_Body; + + Unknown_Device : exception; + -- Raised by the routines below for a device passed as an actual parameter + -- when that device is not present on the given hardware instance. + + procedure Enable_Clock (This : aliased in out GPIO_Port); + procedure Enable_Clock (Point : GPIO_Point); + procedure Enable_Clock (Points : GPIO_Points); + + procedure Reset (This : aliased in out GPIO_Port) + with Inline; + procedure Reset (Point : GPIO_Point) + with Inline; + procedure Reset (Points : GPIO_Points) + with Inline; + + function GPIO_Port_Representation (Port : GPIO_Port) return UInt4 + with Inline; + + GPIO_A : aliased GPIO_Port with Import, Volatile, Address => GPIOA_Base; + GPIO_B : aliased GPIO_Port with Import, Volatile, Address => GPIOB_Base; + GPIO_C : aliased GPIO_Port with Import, Volatile, Address => GPIOC_Base; + GPIO_D : aliased GPIO_Port with Import, Volatile, Address => GPIOD_Base; + GPIO_E : aliased GPIO_Port with Import, Volatile, Address => GPIOE_Base; + GPIO_H : aliased GPIO_Port with Import, Volatile, Address => GPIOH_Base; + + PA0 : aliased GPIO_Point := (GPIO_A'Access, Pin_0); + PA1 : aliased GPIO_Point := (GPIO_A'Access, Pin_1); + PA2 : aliased GPIO_Point := (GPIO_A'Access, Pin_2); + PA3 : aliased GPIO_Point := (GPIO_A'Access, Pin_3); + PA4 : aliased GPIO_Point := (GPIO_A'Access, Pin_4); + PA5 : aliased GPIO_Point := (GPIO_A'Access, Pin_5); + PA6 : aliased GPIO_Point := (GPIO_A'Access, Pin_6); + PA7 : aliased GPIO_Point := (GPIO_A'Access, Pin_7); + PA8 : aliased GPIO_Point := (GPIO_A'Access, Pin_8); + PA9 : aliased GPIO_Point := (GPIO_A'Access, Pin_9); + PA10 : aliased GPIO_Point := (GPIO_A'Access, Pin_10); + PA11 : aliased GPIO_Point := (GPIO_A'Access, Pin_11); + PA12 : aliased GPIO_Point := (GPIO_A'Access, Pin_12); + PA13 : aliased GPIO_Point := (GPIO_A'Access, Pin_13); + PA14 : aliased GPIO_Point := (GPIO_A'Access, Pin_14); + PA15 : aliased GPIO_Point := (GPIO_A'Access, Pin_15); + PB0 : aliased GPIO_Point := (GPIO_B'Access, Pin_0); + PB1 : aliased GPIO_Point := (GPIO_B'Access, Pin_1); + PB2 : aliased GPIO_Point := (GPIO_B'Access, Pin_2); + PB3 : aliased GPIO_Point := (GPIO_B'Access, Pin_3); + PB4 : aliased GPIO_Point := (GPIO_B'Access, Pin_4); + PB5 : aliased GPIO_Point := (GPIO_B'Access, Pin_5); + PB6 : aliased GPIO_Point := (GPIO_B'Access, Pin_6); + PB7 : aliased GPIO_Point := (GPIO_B'Access, Pin_7); + PB8 : aliased GPIO_Point := (GPIO_B'Access, Pin_8); + PB9 : aliased GPIO_Point := (GPIO_B'Access, Pin_9); + PB10 : aliased GPIO_Point := (GPIO_B'Access, Pin_10); + PB11 : aliased GPIO_Point := (GPIO_B'Access, Pin_11); + PB12 : aliased GPIO_Point := (GPIO_B'Access, Pin_12); + PB13 : aliased GPIO_Point := (GPIO_B'Access, Pin_13); + PB14 : aliased GPIO_Point := (GPIO_B'Access, Pin_14); + PB15 : aliased GPIO_Point := (GPIO_B'Access, Pin_15); + PC0 : aliased GPIO_Point := (GPIO_C'Access, Pin_0); + PC1 : aliased GPIO_Point := (GPIO_C'Access, Pin_1); + PC2 : aliased GPIO_Point := (GPIO_C'Access, Pin_2); + PC3 : aliased GPIO_Point := (GPIO_C'Access, Pin_3); + PC4 : aliased GPIO_Point := (GPIO_C'Access, Pin_4); + PC5 : aliased GPIO_Point := (GPIO_C'Access, Pin_5); + PC6 : aliased GPIO_Point := (GPIO_C'Access, Pin_6); + PC7 : aliased GPIO_Point := (GPIO_C'Access, Pin_7); + PC8 : aliased GPIO_Point := (GPIO_C'Access, Pin_8); + PC9 : aliased GPIO_Point := (GPIO_C'Access, Pin_9); + PC10 : aliased GPIO_Point := (GPIO_C'Access, Pin_10); + PC11 : aliased GPIO_Point := (GPIO_C'Access, Pin_11); + PC12 : aliased GPIO_Point := (GPIO_C'Access, Pin_12); + PC13 : aliased GPIO_Point := (GPIO_C'Access, Pin_13); + PC14 : aliased GPIO_Point := (GPIO_C'Access, Pin_14); + PC15 : aliased GPIO_Point := (GPIO_C'Access, Pin_15); + PD0 : aliased GPIO_Point := (GPIO_D'Access, Pin_0); + PD1 : aliased GPIO_Point := (GPIO_D'Access, Pin_1); + PD2 : aliased GPIO_Point := (GPIO_D'Access, Pin_2); + PD3 : aliased GPIO_Point := (GPIO_D'Access, Pin_3); + PD4 : aliased GPIO_Point := (GPIO_D'Access, Pin_4); + PD5 : aliased GPIO_Point := (GPIO_D'Access, Pin_5); + PD6 : aliased GPIO_Point := (GPIO_D'Access, Pin_6); + PD7 : aliased GPIO_Point := (GPIO_D'Access, Pin_7); + PD8 : aliased GPIO_Point := (GPIO_D'Access, Pin_8); + PD9 : aliased GPIO_Point := (GPIO_D'Access, Pin_9); + PD10 : aliased GPIO_Point := (GPIO_D'Access, Pin_10); + PD11 : aliased GPIO_Point := (GPIO_D'Access, Pin_11); + PD12 : aliased GPIO_Point := (GPIO_D'Access, Pin_12); + PD13 : aliased GPIO_Point := (GPIO_D'Access, Pin_13); + PD14 : aliased GPIO_Point := (GPIO_D'Access, Pin_14); + PD15 : aliased GPIO_Point := (GPIO_D'Access, Pin_15); + PE0 : aliased GPIO_Point := (GPIO_E'Access, Pin_0); + PE1 : aliased GPIO_Point := (GPIO_E'Access, Pin_1); + PE2 : aliased GPIO_Point := (GPIO_E'Access, Pin_2); + PE3 : aliased GPIO_Point := (GPIO_E'Access, Pin_3); + PE4 : aliased GPIO_Point := (GPIO_E'Access, Pin_4); + PE5 : aliased GPIO_Point := (GPIO_E'Access, Pin_5); + PE6 : aliased GPIO_Point := (GPIO_E'Access, Pin_6); + PE7 : aliased GPIO_Point := (GPIO_E'Access, Pin_7); + PE8 : aliased GPIO_Point := (GPIO_E'Access, Pin_8); + PE9 : aliased GPIO_Point := (GPIO_E'Access, Pin_9); + PE10 : aliased GPIO_Point := (GPIO_E'Access, Pin_10); + PE11 : aliased GPIO_Point := (GPIO_E'Access, Pin_11); + PE12 : aliased GPIO_Point := (GPIO_E'Access, Pin_12); + PE13 : aliased GPIO_Point := (GPIO_E'Access, Pin_13); + PE14 : aliased GPIO_Point := (GPIO_E'Access, Pin_14); + PE15 : aliased GPIO_Point := (GPIO_E'Access, Pin_15); + PH0 : aliased GPIO_Point := (GPIO_H'Access, Pin_0); + PH1 : aliased GPIO_Point := (GPIO_H'Access, Pin_1); + PH2 : aliased GPIO_Point := (GPIO_H'Access, Pin_2); + PH3 : aliased GPIO_Point := (GPIO_H'Access, Pin_3); + PH4 : aliased GPIO_Point := (GPIO_H'Access, Pin_4); + PH5 : aliased GPIO_Point := (GPIO_H'Access, Pin_5); + PH6 : aliased GPIO_Point := (GPIO_H'Access, Pin_6); + PH7 : aliased GPIO_Point := (GPIO_H'Access, Pin_7); + PH8 : aliased GPIO_Point := (GPIO_H'Access, Pin_8); + PH9 : aliased GPIO_Point := (GPIO_H'Access, Pin_9); + PH10 : aliased GPIO_Point := (GPIO_H'Access, Pin_10); + PH11 : aliased GPIO_Point := (GPIO_H'Access, Pin_11); + PH12 : aliased GPIO_Point := (GPIO_H'Access, Pin_12); + PH13 : aliased GPIO_Point := (GPIO_H'Access, Pin_13); + PH14 : aliased GPIO_Point := (GPIO_H'Access, Pin_14); + PH15 : aliased GPIO_Point := (GPIO_H'Access, Pin_15); + + GPIO_AF_RTC_50Hz_0 : constant GPIO_Alternate_Function; + GPIO_AF_MCO_0 : constant GPIO_Alternate_Function; + GPIO_AF_TAMPER_0 : constant GPIO_Alternate_Function; + GPIO_AF_SWJ_0 : constant GPIO_Alternate_Function; + GPIO_AF_TRACE_0 : constant GPIO_Alternate_Function; + GPIO_AF_TIM1_1 : constant GPIO_Alternate_Function; + GPIO_AF_TIM2_1 : constant GPIO_Alternate_Function; + GPIO_AF_TIM3_2 : constant GPIO_Alternate_Function; + GPIO_AF_TIM4_2 : constant GPIO_Alternate_Function; + GPIO_AF_TIM5_2 : constant GPIO_Alternate_Function; + GPIO_AF_TIM8_3 : constant GPIO_Alternate_Function; + GPIO_AF_TIM9_3 : constant GPIO_Alternate_Function; + GPIO_AF_TIM10_3 : constant GPIO_Alternate_Function; + GPIO_AF_TIM11_3 : constant GPIO_Alternate_Function; + GPIO_AF_I2C1_4 : constant GPIO_Alternate_Function; + GPIO_AF_I2C2_4 : constant GPIO_Alternate_Function; + GPIO_AF_I2C3_4 : constant GPIO_Alternate_Function; + GPIO_AF_SPI1_5 : constant GPIO_Alternate_Function; + GPIO_AF_SPI2_5 : constant GPIO_Alternate_Function; + GPIO_AF_I2S2_5 : constant GPIO_Alternate_Function; + GPIO_AF_I2S2ext_5 : constant GPIO_Alternate_Function; + GPIO_AF_SPI3_6 : constant GPIO_Alternate_Function; + GPIO_AF_I2S3_6 : constant GPIO_Alternate_Function; + GPIO_AF_I2Sext_6 : constant GPIO_Alternate_Function; + GPIO_AF_I2S3ext_7 : constant GPIO_Alternate_Function; + GPIO_AF_USART1_7 : constant GPIO_Alternate_Function; + GPIO_AF_USART2_7 : constant GPIO_Alternate_Function; + GPIO_AF_USART3_7 : constant GPIO_Alternate_Function; + GPIO_AF_UART4_8 : constant GPIO_Alternate_Function; + GPIO_AF_UART5_8 : constant GPIO_Alternate_Function; + GPIO_AF_USART6_8 : constant GPIO_Alternate_Function; + GPIO_AF_CAN1_9 : constant GPIO_Alternate_Function; + GPIO_AF_CAN2_9 : constant GPIO_Alternate_Function; + GPIO_AF_TIM12_9 : constant GPIO_Alternate_Function; + GPIO_AF_TIM13_9 : constant GPIO_Alternate_Function; + GPIO_AF_TIM14_9 : constant GPIO_Alternate_Function; + GPIO_AF_OTG_FS_10 : constant GPIO_Alternate_Function; + GPIO_AF_OTG_HS_10 : constant GPIO_Alternate_Function; + GPIO_AF_ETH_11 : constant GPIO_Alternate_Function; + GPIO_AF_FMC_12 : constant GPIO_Alternate_Function; + GPIO_AF_OTG_FS_12 : constant GPIO_Alternate_Function; + GPIO_AF_SDIO_12 : constant GPIO_Alternate_Function; + GPIO_AF_DCMI_13 : constant GPIO_Alternate_Function; + GPIO_AF_EVENTOUT_15 : constant GPIO_Alternate_Function; + + ADC_1 : aliased Analog_To_Digital_Converter with Volatile, Import, Address => ADC1_Base; + + VBat : constant ADC_Point := (ADC_1'Access, Channel => VBat_Channel); + + Temperature_Channel : constant TemperatureSensor_Channel := 16; + Temperature_Sensor : constant ADC_Point := + (ADC_1'Access, Channel => Temperature_Channel); + -- see RM pg 410, section 13.10, also pg 389 + + VBat_Bridge_Divisor : constant := 2; + -- The VBAT pin is internally connected to a bridge divider. The actual + -- voltage is the raw conversion value * the divisor. See section 13.11, + -- pg 412 of the RM. + + procedure Enable_Clock (This : aliased in out Analog_To_Digital_Converter); + + procedure Reset_All_ADC_Units; + + Internal_USART_1 : aliased Internal_USART with Import, Volatile, Address => USART1_Base; + Internal_USART_2 : aliased Internal_USART with Import, Volatile, Address => USART2_Base; + Internal_USART_6 : aliased Internal_USART with Import, Volatile, Address => USART6_Base; + + USART_1 : aliased USART (Internal_USART_1'Access); + USART_2 : aliased USART (Internal_USART_2'Access); + USART_6 : aliased USART (Internal_USART_6'Access); + + procedure Enable_Clock (This : aliased in out USART); + + procedure Reset (This : aliased in out USART); + + DMA_1 : aliased DMA_Controller with Import, Volatile, Address => DMA1_Base; + DMA_2 : aliased DMA_Controller with Import, Volatile, Address => DMA2_Base; + + procedure Enable_Clock (This : aliased in out DMA_Controller); + procedure Reset (This : aliased in out DMA_Controller); + + Internal_I2C_Port_1 : aliased Internal_I2C_Port with Import, Volatile, Address => I2C1_Base; + Internal_I2C_Port_2 : aliased Internal_I2C_Port with Import, Volatile, Address => I2C2_Base; + Internal_I2C_Port_3 : aliased Internal_I2C_Port with Import, Volatile, Address => I2C3_Base; + + type I2C_Port_Id is (I2C_Id_1, I2C_Id_2, I2C_Id_3); + + I2C_1 : aliased I2C_Port (Internal_I2C_Port_1'Access); + I2C_2 : aliased I2C_Port (Internal_I2C_Port_2'Access); + I2C_3 : aliased I2C_Port (Internal_I2C_Port_3'Access); + + I2C_1_DMA : aliased I2C_Port_DMA (Internal_I2C_Port_1'Access); + I2C_2_DMA : aliased I2C_Port_DMA (Internal_I2C_Port_2'Access); + I2C_3_DMA : aliased I2C_Port_DMA (Internal_I2C_Port_3'Access); + + function As_Port_Id (Port : I2C_Port'Class) return I2C_Port_Id with Inline; + + procedure Enable_Clock (This : aliased I2C_Port'Class); + procedure Enable_Clock (This : I2C_Port_Id); + + procedure Reset (This : I2C_Port'Class); + procedure Reset (This : I2C_Port_Id); + + Internal_SPI_1 : aliased Internal_SPI_Port with Import, Volatile, Address => SPI1_Base; + Internal_SPI_2 : aliased Internal_SPI_Port with Import, Volatile, Address => SPI2_Base; + Internal_SPI_3 : aliased Internal_SPI_Port with Import, Volatile, Address => SPI3_Base; + + SPI_1 : aliased SPI_Port (Internal_SPI_1'Access); + SPI_2 : aliased SPI_Port (Internal_SPI_2'Access); + SPI_3 : aliased SPI_Port (Internal_SPI_3'Access); + + SPI_1_DMA : aliased SPI_Port_DMA (Internal_SPI_1'Access); + SPI_2_DMA : aliased SPI_Port_DMA (Internal_SPI_2'Access); + SPI_3_DMA : aliased SPI_Port_DMA (Internal_SPI_3'Access); + + procedure Enable_Clock (This : SPI_Port'Class); + procedure Reset (This : in out SPI_Port'Class); + + Internal_I2S_1 : aliased Internal_I2S_Port with Import, Volatile, Address => SPI1_Base; + Internal_I2S_2 : aliased Internal_I2S_Port with Import, Volatile, Address => SPI2_Base; + Internal_I2S_3 : aliased Internal_I2S_Port with Import, Volatile, Address => SPI3_Base; + Internal_I2S_2_Ext : aliased Internal_I2S_Port with Import, Volatile, Address => I2S2ext_Base; + Internal_I2S_3_Ext : aliased Internal_I2S_Port with Import, Volatile, Address => I2S3ext_Base; + + I2S_1 : aliased I2S_Port (Internal_I2S_1'Access, Extended => False); + I2S_2 : aliased I2S_Port (Internal_I2S_2'Access, Extended => False); + I2S_3 : aliased I2S_Port (Internal_I2S_3'Access, Extended => False); + + I2S_2_Ext : aliased I2S_Port (Internal_I2S_2_Ext'Access, Extended => True); + I2S_3_Ext : aliased I2S_Port (Internal_I2S_3_Ext'Access, Extended => True); + + procedure Enable_Clock (This : I2S_Port); + procedure Reset (This : in out I2S_Port); + + Timer_1 : aliased Timer with Import, Volatile, Address => TIM1_Base; + Timer_2 : aliased Timer with Import, Volatile, Address => TIM2_Base; + Timer_3 : aliased Timer with Import, Volatile, Address => TIM3_Base; + Timer_4 : aliased Timer with Import, Volatile, Address => TIM4_Base; + Timer_5 : aliased Timer with Import, Volatile, Address => TIM5_Base; + Timer_8 : aliased Timer with Import, Volatile, Address => TIM8_Base; + Timer_9 : aliased Timer with Import, Volatile, Address => TIM9_Base; + Timer_10 : aliased Timer with Import, Volatile, Address => TIM10_Base; + Timer_11 : aliased Timer with Import, Volatile, Address => TIM11_Base; + + procedure Enable_Clock (This : in out Timer); + + procedure Reset (This : in out Timer); + + ----------- + -- SDMMC -- + ----------- + + SDIO : aliased SDMMC_Controller (STM32_SVD.SDIO.SDIO_Periph'Access); + + type SDIO_Clock_Source is (Src_Sysclk, Src_48Mhz); + + procedure Enable_Clock (This : in out SDMMC_Controller); + procedure Reset (This : in out SDMMC_Controller); + + --------- + -- CRC -- + --------- + + CRC_Unit : CRC_32 with Import, Volatile, Address => CRC_Base; + + procedure Enable_Clock (This : in out CRC_32); + + procedure Disable_Clock (This : in out CRC_32); + + procedure Reset (This : in out CRC_32); + + ----------------------------- + -- Reset and Clock Control -- + ----------------------------- + + type RCC_System_Clocks is record + SYSCLK : UInt32; + HCLK : UInt32; + PCLK1 : UInt32; + PCLK2 : UInt32; + TIMCLK1 : UInt32; + TIMCLK2 : UInt32; + I2SCLK : UInt32; + end record; + + function System_Clock_Frequencies return RCC_System_Clocks; + + procedure Set_PLLI2S_Factors (Pll_N : UInt9; + Pll_R : UInt3); + + function PLLI2S_Enabled return Boolean; + + procedure Enable_PLLI2S + with Post => PLLI2S_Enabled; + + procedure Disable_PLLI2S + with Post => not PLLI2S_Enabled; + + RTC : aliased RTC_Device; + +private + + GPIO_AF_RTC_50Hz_0 : constant GPIO_Alternate_Function := 0; + GPIO_AF_MCO_0 : constant GPIO_Alternate_Function := 0; + GPIO_AF_TAMPER_0 : constant GPIO_Alternate_Function := 0; + GPIO_AF_SWJ_0 : constant GPIO_Alternate_Function := 0; + GPIO_AF_TRACE_0 : constant GPIO_Alternate_Function := 0; + GPIO_AF_TIM1_1 : constant GPIO_Alternate_Function := 1; + GPIO_AF_TIM2_1 : constant GPIO_Alternate_Function := 1; + GPIO_AF_TIM3_2 : constant GPIO_Alternate_Function := 2; + GPIO_AF_TIM4_2 : constant GPIO_Alternate_Function := 2; + GPIO_AF_TIM5_2 : constant GPIO_Alternate_Function := 2; + GPIO_AF_TIM8_3 : constant GPIO_Alternate_Function := 3; + GPIO_AF_TIM9_3 : constant GPIO_Alternate_Function := 3; + GPIO_AF_TIM10_3 : constant GPIO_Alternate_Function := 3; + GPIO_AF_TIM11_3 : constant GPIO_Alternate_Function := 3; + GPIO_AF_I2C1_4 : constant GPIO_Alternate_Function := 4; + GPIO_AF_I2C2_4 : constant GPIO_Alternate_Function := 4; + GPIO_AF_I2C3_4 : constant GPIO_Alternate_Function := 4; + GPIO_AF_SPI1_5 : constant GPIO_Alternate_Function := 5; + GPIO_AF_SPI2_5 : constant GPIO_Alternate_Function := 5; + GPIO_AF_I2S2_5 : constant GPIO_Alternate_Function := 5; + GPIO_AF_I2S2ext_5 : constant GPIO_Alternate_Function := 5; + GPIO_AF_SPI3_6 : constant GPIO_Alternate_Function := 6; + GPIO_AF_I2S3_6 : constant GPIO_Alternate_Function := 6; + GPIO_AF_I2Sext_6 : constant GPIO_Alternate_Function := 6; + GPIO_AF_I2S3ext_7 : constant GPIO_Alternate_Function := 7; + GPIO_AF_USART1_7 : constant GPIO_Alternate_Function := 7; + GPIO_AF_USART2_7 : constant GPIO_Alternate_Function := 7; + GPIO_AF_USART3_7 : constant GPIO_Alternate_Function := 7; + GPIO_AF_UART4_8 : constant GPIO_Alternate_Function := 8; + GPIO_AF_UART5_8 : constant GPIO_Alternate_Function := 8; + GPIO_AF_USART6_8 : constant GPIO_Alternate_Function := 8; + GPIO_AF_CAN1_9 : constant GPIO_Alternate_Function := 9; + GPIO_AF_CAN2_9 : constant GPIO_Alternate_Function := 9; + GPIO_AF_TIM12_9 : constant GPIO_Alternate_Function := 9; + GPIO_AF_TIM13_9 : constant GPIO_Alternate_Function := 9; + GPIO_AF_TIM14_9 : constant GPIO_Alternate_Function := 9; + GPIO_AF_OTG_FS_10 : constant GPIO_Alternate_Function := 10; + GPIO_AF_OTG_HS_10 : constant GPIO_Alternate_Function := 10; + GPIO_AF_ETH_11 : constant GPIO_Alternate_Function := 11; + GPIO_AF_FMC_12 : constant GPIO_Alternate_Function := 12; + GPIO_AF_OTG_FS_12 : constant GPIO_Alternate_Function := 12; + GPIO_AF_SDIO_12 : constant GPIO_Alternate_Function := 12; + GPIO_AF_DCMI_13 : constant GPIO_Alternate_Function := 13; + GPIO_AF_EVENTOUT_15 : constant GPIO_Alternate_Function := 15; + +end STM32.Device; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-pwm.adb b/arch/ARM/STM32/devices/stm32f401/stm32-pwm.adb new file mode 100644 index 000000000..46fac00ac --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-pwm.adb @@ -0,0 +1,436 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2017, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System; use System; +with STM32_SVD; use STM32_SVD; +with STM32.Device; use STM32.Device; + +package body STM32.PWM is + + procedure Compute_Prescalar_And_Period + (This : access Timer; + Requested_Frequency : Hertz; + Prescalar : out UInt32; + Period : out UInt32) + with Pre => Requested_Frequency > 0; + -- Computes the minimum prescaler and thus the maximum resolution for the + -- given timer, based on the system clocks and the requested frequency. + -- Computes the period required for the requested frequency. + + function Timer_Period (This : PWM_Modulator) return UInt32 is + (Current_Autoreload (This.Generator.all)); + + procedure Configure_PWM_GPIO + (Output : GPIO_Point; + PWM_AF : GPIO_Alternate_Function; + AF_Speed : Pin_Output_Speeds); + + -- TODO: move these two functions to the STM32.Device packages? + function Has_APB2_Frequency (This : Timer) return Boolean; + -- timers 1, 8, 9, 10, 11 + + function Has_APB1_Frequency (This : Timer) return Boolean; + -- timers 3, 4, 6, 7, 12, 13, 14 + + -------------------- + -- Set_Duty_Cycle -- + -------------------- + + procedure Set_Duty_Cycle + (This : in out PWM_Modulator; + Value : Percentage) + is + Pulse16 : UInt16; + Pulse32 : UInt32; + begin + This.Duty_Cycle := Value; + + if Value = 0 then + Set_Compare_Value (This.Generator.all, This.Channel, UInt16'(0)); + else + -- for a Value of 0, the computation of Pulse wraps around, so we + -- only compute it when not zero + + if Has_32bit_CC_Values (This.Generator.all) then + Pulse32 := UInt32 ((Timer_Period (This) + 1) * UInt32 (Value) / 100) - 1; + Set_Compare_Value (This.Generator.all, This.Channel, Pulse32); + else + Pulse16 := UInt16 ((Timer_Period (This) + 1) * UInt32 (Value) / 100) - 1; + Set_Compare_Value (This.Generator.all, This.Channel, Pulse16); + end if; + end if; + end Set_Duty_Cycle; + + ------------------- + -- Set_Duty_Time -- + ------------------- + + procedure Set_Duty_Time + (This : in out PWM_Modulator; + Value : Microseconds) + is + Pulse16 : UInt16; + Pulse32 : UInt32; + Period : constant UInt32 := Timer_Period (This) + 1; + uS_Per_Period : constant UInt32 := Microseconds_Per_Period (This); + begin + if Value = 0 then + Set_Compare_Value (This.Generator.all, This.Channel, UInt16'(0)); + else + -- for a Value of 0, the computation of Pulse wraps around, so we + -- only compute it when not zero + if Has_32bit_CC_Values (This.Generator.all) then + Pulse32 := UInt32 ((Period / uS_Per_Period) * Value) - 1; + Set_Compare_Value (This.Generator.all, This.Channel, Pulse32); + else + Pulse16 := UInt16 ((Period * Value) / uS_Per_Period) - 1; + Set_Compare_Value (This.Generator.all, This.Channel, Pulse16); + end if; + end if; + end Set_Duty_Time; + + ------------------------ + -- Current_Duty_Cycle -- + ------------------------ + + function Current_Duty_Cycle (This : PWM_Modulator) return Percentage is + begin + return This.Duty_Cycle; + end Current_Duty_Cycle; + + ------------------------- + -- Configure_PWM_Timer -- + ------------------------- + + procedure Configure_PWM_Timer + (Generator : not null access Timer; + Frequency : Hertz) + is + Computed_Prescalar : UInt32; + Computed_Period : UInt32; + begin + Enable_Clock (Generator.all); + + Compute_Prescalar_And_Period + (Generator, + Requested_Frequency => Frequency, + Prescalar => Computed_Prescalar, + Period => Computed_Period); + + Computed_Period := Computed_Period - 1; + + Configure + (Generator.all, + Prescaler => UInt16 (Computed_Prescalar), + Period => Computed_Period, + Clock_Divisor => Div1, + Counter_Mode => Up); + + Set_Autoreload_Preload (Generator.all, True); + + if Advanced_Timer (Generator.all) then + Enable_Main_Output (Generator.all); + end if; + + Enable (Generator.all); + end Configure_PWM_Timer; + + ------------------------ + -- Attach_PWM_Channel -- + ------------------------ + + procedure Attach_PWM_Channel + (This : in out PWM_Modulator; + Generator : not null access Timer; + Channel : Timer_Channel; + Point : GPIO_Point; + PWM_AF : GPIO_Alternate_Function; + Polarity : Timer_Output_Compare_Polarity := High; + AF_Speed : Pin_Output_Speeds := Speed_100MHz) + is + begin + This.Channel := Channel; + This.Generator := Generator; + + Enable_Clock (Point); + + Configure_PWM_GPIO (Point, PWM_AF, AF_Speed); + + Configure_Channel_Output + (This.Generator.all, + Channel => Channel, + Mode => PWM1, + State => Disable, + Pulse => 0, + Polarity => Polarity); + + Set_Compare_Value (This.Generator.all, Channel, UInt16 (0)); + + Disable_Channel (This.Generator.all, Channel); + end Attach_PWM_Channel; + + ------------------------ + -- Attach_PWM_Channel -- + ------------------------ + + procedure Attach_PWM_Channel + (This : in out PWM_Modulator; + Generator : not null access Timer; + Channel : Timer_Channel; + Point : GPIO_Point; + Complementary_Point : GPIO_Point; + PWM_AF : GPIO_Alternate_Function; + Polarity : Timer_Output_Compare_Polarity; + Idle_State : Timer_Capture_Compare_State; + Complementary_Polarity : Timer_Output_Compare_Polarity; + Complementary_Idle_State : Timer_Capture_Compare_State; + AF_Speed : Pin_Output_Speeds := Speed_100MHz) + is + begin + This.Channel := Channel; + This.Generator := Generator; + + Enable_Clock (Point); + Enable_Clock (Complementary_Point); + + Configure_PWM_GPIO (Point, PWM_AF, AF_Speed); + Configure_PWM_GPIO (Complementary_Point, PWM_AF, AF_Speed); + + Configure_Channel_Output + (This.Generator.all, + Channel => Channel, + Mode => PWM1, + State => Disable, + Pulse => 0, + Polarity => Polarity, + Idle_State => Idle_State, + Complementary_Polarity => Complementary_Polarity, + Complementary_Idle_State => Complementary_Idle_State); + + Set_Compare_Value (This.Generator.all, Channel, UInt16 (0)); + + Disable_Channel (This.Generator.all, Channel); + end Attach_PWM_Channel; + + ------------------- + -- Enable_Output -- + ------------------- + + procedure Enable_Output (This : in out PWM_Modulator) is + begin + Enable_Channel (This.Generator.all, This.Channel); + end Enable_Output; + + --------------------------------- + -- Enable_Complementary_Output -- + --------------------------------- + + procedure Enable_Complementary_Output (This : in out PWM_Modulator) is + begin + Enable_Complementary_Channel (This.Generator.all, This.Channel); + end Enable_Complementary_Output; + + -------------------- + -- Output_Enabled -- + -------------------- + + function Output_Enabled (This : PWM_Modulator) return Boolean is + begin + return Channel_Enabled (This.Generator.all, This.Channel); + end Output_Enabled; + + ---------------------------------- + -- Complementary_Output_Enabled -- + ---------------------------------- + + function Complementary_Output_Enabled (This : PWM_Modulator) return Boolean is + begin + return Complementary_Channel_Enabled (This.Generator.all, This.Channel); + end Complementary_Output_Enabled; + + -------------------- + -- Disable_Output -- + -------------------- + + procedure Disable_Output (This : in out PWM_Modulator) is + begin + Disable_Channel (This.Generator.all, This.Channel); + end Disable_Output; + + ---------------------------------- + -- Disable_Complementary_Output -- + ---------------------------------- + + procedure Disable_Complementary_Output (This : in out PWM_Modulator) is + begin + Disable_Complementary_Channel (This.Generator.all, This.Channel); + end Disable_Complementary_Output; + + ------------------ + -- Set_Polarity -- + ------------------ + + procedure Set_Polarity + (This : in PWM_Modulator; + Polarity : in Timer_Output_Compare_Polarity) is + begin + Set_Output_Polarity (This.Generator.all, This.Channel, Polarity); + end Set_Polarity; + + -------------------------------- + -- Set_Complementary_Polarity -- + -------------------------------- + + procedure Set_Complementary_Polarity + (This : in PWM_Modulator; + Polarity : in Timer_Output_Compare_Polarity) is + begin + Set_Output_Complementary_Polarity (This.Generator.all, This.Channel, Polarity); + end Set_Complementary_Polarity; + + ------------------------ + -- Configure_PWM_GPIO -- + ------------------------ + + procedure Configure_PWM_GPIO + (Output : GPIO_Point; + PWM_AF : GPIO_Alternate_Function; + AF_Speed : Pin_Output_Speeds) + is + begin + Output.Configure_IO + ((Mode_AF, + AF => PWM_AF, + Resistors => Floating, + AF_Output_Type => Push_Pull, + AF_Speed => AF_Speed)); + end Configure_PWM_GPIO; + + ---------------------------------- + -- Compute_Prescalar_and_Period -- + ---------------------------------- + + procedure Compute_Prescalar_And_Period + (This : access Timer; + Requested_Frequency : Hertz; + Prescalar : out UInt32; + Period : out UInt32) + is + Max_Prescalar : constant := 16#FFFF#; + Max_Period : UInt32; + Hardware_Frequency : UInt32; + Clocks : constant RCC_System_Clocks := System_Clock_Frequencies; + CK_CNT : UInt32; + begin + if Has_APB1_Frequency (This.all) then + Hardware_Frequency := Clocks.TIMCLK1; + elsif Has_APB2_Frequency (This.all) then + Hardware_Frequency := Clocks.TIMCLK2; + else + raise Unknown_Timer; + end if; + + if Has_32bit_Counter (This.all) then + Max_Period := 16#FFFF_FFFF#; + else + Max_Period := 16#FFFF#; + end if; + + if Requested_Frequency > Hardware_Frequency then + raise Invalid_Request with "Freq too high"; + end if; + + Prescalar := 0; + loop + -- Compute the Counter's clock + CK_CNT := Hardware_Frequency / (Prescalar + 1); + -- Determine the CK_CNT periods to achieve the requested frequency + Period := CK_CNT / Requested_Frequency; + + exit when not + ((Period > Max_Period) and + (Prescalar <= Max_Prescalar)); + + Prescalar := Prescalar + 1; + end loop; + + if Prescalar > Max_Prescalar then + raise Invalid_Request with "Freq too low"; + end if; + end Compute_Prescalar_And_Period; + + ----------------------------- + -- Microseconds_Per_Period -- + ----------------------------- + + function Microseconds_Per_Period (This : PWM_Modulator) return Microseconds is + Result : UInt32; + Counter_Frequency : UInt32; + Platform_Frequency : UInt32; + + Clocks : constant RCC_System_Clocks := System_Clock_Frequencies; + Period : constant UInt32 := Timer_Period (This) + 1; + Prescalar : constant UInt16 := Current_Prescaler (This.Generator.all) + 1; + begin + if Has_APB1_Frequency (This.Generator.all) then + Platform_Frequency := Clocks.TIMCLK1; + else + Platform_Frequency := Clocks.TIMCLK2; + end if; + + Counter_Frequency := (Platform_Frequency / UInt32 (Prescalar)) / Period; + + Result := 1_000_000 / Counter_Frequency; + return Result; + end Microseconds_Per_Period; + + ------------------------ + -- Has_APB2_Frequency -- + ------------------------ + + function Has_APB2_Frequency (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM8_Base or + This'Address = STM32_SVD.TIM9_Base or + This'Address = STM32_SVD.TIM10_Base or + This'Address = STM32_SVD.TIM11_Base); + + ------------------------ + -- Has_APB1_Frequency -- + ------------------------ + + function Has_APB1_Frequency (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base); + +end STM32.PWM; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-rcc.adb b/arch/ARM/STM32/devices/stm32f401/stm32-rcc.adb new file mode 100644 index 000000000..ee48aa475 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-rcc.adb @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with Ada.Unchecked_Conversion; +with STM32.Device; use STM32.Device; +with STM32_SVD.PWR; use STM32_SVD.PWR; +with STM32_SVD.RCC; use STM32_SVD.RCC; + +package body STM32.RCC is + + function To_AHB1RSTR_T is new Ada.Unchecked_Conversion + (UInt32, AHB1RSTR_Register); + function To_AHB2RSTR_T is new Ada.Unchecked_Conversion + (UInt32, AHB2RSTR_Register); + function To_APB1RSTR_T is new Ada.Unchecked_Conversion + (UInt32, APB1RSTR_Register); + function To_APB2RSTR_T is new Ada.Unchecked_Conversion + (UInt32, APB2RSTR_Register); + + --------------------------------------------------------------------------- + ------- Enable/Disable/Reset Routines ----------------------------------- + --------------------------------------------------------------------------- + + procedure CRC_Clock_Enable is + begin + RCC_Periph.AHB1ENR.CRCEN := True; + end CRC_Clock_Enable; + + procedure WWDG_Clock_Enable is + begin + RCC_Periph.APB1ENR.WWDGEN := True; + end WWDG_Clock_Enable; + + procedure SYSCFG_Clock_Enable is + begin + RCC_Periph.APB2ENR.SYSCFGEN := True; + end SYSCFG_Clock_Enable; + + procedure AHB1_Force_Reset + is + begin + RCC_Periph.AHB1RSTR := To_AHB1RSTR_T (16#FFFF_FFFF#); + end AHB1_Force_Reset; + + procedure AHB1_Release_Reset is + begin + RCC_Periph.AHB1RSTR := To_AHB1RSTR_T (0); + end AHB1_Release_Reset; + + procedure AHB2_Force_Reset is + begin + RCC_Periph.AHB2RSTR := To_AHB2RSTR_T (16#FFFF_FFFF#); + end AHB2_Force_Reset; + + procedure AHB2_Release_Reset is + begin + RCC_Periph.AHB2RSTR := To_AHB2RSTR_T (0); + end AHB2_Release_Reset; + + procedure APB1_Force_Reset is + begin + RCC_Periph.APB1RSTR := To_APB1RSTR_T (16#FFFF_FFFF#); + end APB1_Force_Reset; + + procedure APB1_Release_Reset is + begin + RCC_Periph.APB1RSTR := To_APB1RSTR_T (0); + end APB1_Release_Reset; + + procedure APB2_Force_Reset is + begin + RCC_Periph.APB2RSTR := To_APB2RSTR_T (16#FFFF_FFFF#); + end APB2_Force_Reset; + + procedure APB2_Release_Reset is + begin + RCC_Periph.APB2RSTR := To_APB2RSTR_T (0); + end APB2_Release_Reset; + + procedure CRC_Force_Reset is + begin + RCC_Periph.AHB1RSTR.CRCRST := True; + end CRC_Force_Reset; + + procedure CRC_Release_Reset is + begin + RCC_Periph.AHB1RSTR.CRCRST := False; + end CRC_Release_Reset; + + procedure OTGFS_Force_Reset is + begin + RCC_Periph.AHB2RSTR.OTGFSRST := True; + end OTGFS_Force_Reset; + + procedure OTGFS_Release_Reset is + begin + RCC_Periph.AHB2RSTR.OTGFSRST := False; + end OTGFS_Release_Reset; + + procedure WWDG_Force_Reset is + begin + RCC_Periph.APB1RSTR.WWDGRST := True; + end WWDG_Force_Reset; + + procedure WWDG_Release_Reset is + begin + RCC_Periph.APB1RSTR.WWDGRST := False; + end WWDG_Release_Reset; + + procedure SYSCFG_Force_Reset is + begin + RCC_Periph.APB2RSTR.SYSCFGRST := True; + end SYSCFG_Force_Reset; + + procedure SYSCFG_Release_Reset is + begin + RCC_Periph.APB2RSTR.SYSCFGRST := False; + end SYSCFG_Release_Reset; + +end STM32.RCC; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-rcc.ads b/arch/ARM/STM32/devices/stm32f401/stm32-rcc.ads new file mode 100644 index 000000000..0a0afdbc4 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-rcc.ads @@ -0,0 +1,83 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ +pragma Restrictions (No_Elaboration_Code); + +package STM32.RCC is + +-- type RCC_System_Clocks is record +-- SYSCLK : UInt32; +-- HCLK : UInt32; +-- PCLK1 : UInt32; +-- PCLK2 : UInt32; +-- TIMCLK1 : UInt32; +-- TIMCLK2 : UInt32; +-- end record; +-- +-- function System_Clock_Frequencies return RCC_System_Clocks; + + -- Part below is obsolete and should be moved to the corresponding driver. + + procedure CRC_Clock_Enable with Inline; +-- procedure CCMDATARAMEN_Clock_Enable with Inline; +-- procedure DMA2D_Clock_Enable with Inline; + procedure WWDG_Clock_Enable with Inline; + +-- procedure SDIO_Clock_Enable with Inline; + procedure SYSCFG_Clock_Enable with Inline; + + procedure AHB1_Force_Reset with Inline; + procedure AHB1_Release_Reset with Inline; + procedure AHB2_Force_Reset with Inline; + procedure AHB2_Release_Reset with Inline; + procedure APB1_Force_Reset with Inline; + procedure APB1_Release_Reset with Inline; + procedure APB2_Force_Reset with Inline; + procedure APB2_Release_Reset with Inline; + + procedure CRC_Force_Reset with Inline; + procedure CRC_Release_Reset with Inline; + +-- procedure DMA2D_Force_Reset with Inline; +-- procedure DMA2D_Release_Reset with Inline; + + procedure OTGFS_Force_Reset with Inline; + procedure OTGFS_Release_Reset with Inline; + + procedure WWDG_Force_Reset with Inline; + procedure WWDG_Release_Reset with Inline; + +-- procedure SDIO_Force_Reset with Inline; +-- procedure SDIO_Release_Reset with Inline; + + procedure SYSCFG_Force_Reset with Inline; + procedure SYSCFG_Release_Reset with Inline; + +end STM32.RCC; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-timers.adb b/arch/ARM/STM32/devices/stm32f401/stm32-timers.adb new file mode 100644 index 000000000..427881c01 --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-timers.adb @@ -0,0 +1,1546 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_tim.c -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief timers HAL module driver. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +package body STM32.Timers is + + + function Basic_Timer (This : Timer) return Boolean + is + pragma Unreferenced (This); + begin + return False; + end Basic_Timer; + + --------------- + -- Configure -- + --------------- + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32) + is + begin + This.ARR := Period; + This.Prescaler := Prescaler; + end Configure; + + --------------- + -- Configure -- + --------------- + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32; + Clock_Divisor : Timer_Clock_Divisor; + Counter_Mode : Timer_Counter_Alignment_Mode) + is + begin + This.ARR := Period; + This.Prescaler := Prescaler; + This.CR1.Clock_Division := Clock_Divisor; + This.CR1.Mode_And_Dir := Counter_Mode; + end Configure; + + ---------------------- + -- Set_Counter_Mode -- + ---------------------- + + procedure Set_Counter_Mode + (This : in out Timer; + Value : Timer_Counter_Alignment_Mode) + is + begin + This.CR1.Mode_And_Dir := Value; + end Set_Counter_Mode; + + ------------------------ + -- Set_Clock_Division -- + ------------------------ + + procedure Set_Clock_Division + (This : in out Timer; + Value : Timer_Clock_Divisor) + is + begin + This.CR1.Clock_Division := Value; + end Set_Clock_Division; + + ---------------------------- + -- Current_Clock_Division -- + ---------------------------- + + function Current_Clock_Division (This : Timer) return Timer_Clock_Divisor is + begin + return This.CR1.Clock_Division; + end Current_Clock_Division; + + --------------- + -- Configure -- + --------------- + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32; + Clock_Divisor : Timer_Clock_Divisor; + Counter_Mode : Timer_Counter_Alignment_Mode; + Repetitions : UInt8) + is + begin + This.ARR := Period; + This.Prescaler := Prescaler; + This.CR1.Clock_Division := Clock_Divisor; + This.CR1.Mode_And_Dir := Counter_Mode; + This.RCR := UInt32 (Repetitions); + This.EGR := Immediate'Enum_Rep; + end Configure; + + ------------ + -- Enable -- + ------------ + + procedure Enable (This : in out Timer) is + begin + This.CR1.Timer_Enabled := True; + end Enable; + + ------------- + -- Enabled -- + ------------- + + function Enabled (This : Timer) return Boolean is + begin + return This.CR1.Timer_Enabled; + end Enabled; + + ------------------------ + -- No_Outputs_Enabled -- + ------------------------ + + function No_Outputs_Enabled (This : Timer) return Boolean is + begin + for C in Channel_1 .. Channel_3 loop + if This.CCER (C).CCxE = Enable or This.CCER (C).CCxNE = Enable then + return False; + end if; + end loop; + -- Channel_4 doesn't have the complementary enabler and polarity bits. + -- If it did they would be in the reserved area, which is zero, so we + -- could be tricky and pretend that they exist for this function but + -- doing that would be unnecessarily subtle. The money is on clarity. + if This.CCER (Channel_4).CCxE = Enable then + return False; + end if; + return True; + end No_Outputs_Enabled; + + ------------- + -- Disable -- + ------------- + + procedure Disable (This : in out Timer) is + begin + if No_Outputs_Enabled (This) then + This.CR1.Timer_Enabled := False; + end if; + end Disable; + + ------------------------ + -- Enable_Main_Output -- + ------------------------ + + procedure Enable_Main_Output (This : in out Timer) is + begin + This.BDTR.Main_Output_Enabled := True; + end Enable_Main_Output; + + ------------------------- + -- Disable_Main_Output -- + ------------------------- + + procedure Disable_Main_Output (This : in out Timer) is + begin + if No_Outputs_Enabled (This) then + This.BDTR.Main_Output_Enabled := False; + end if; + end Disable_Main_Output; + + ------------------------- + -- Main_Output_Enabled -- + ------------------------- + + function Main_Output_Enabled (This : Timer) return Boolean is + begin + return This.BDTR.Main_Output_Enabled; + end Main_Output_Enabled; + + ----------------- + -- Set_Counter -- + ----------------- + + procedure Set_Counter (This : in out Timer; Value : UInt16) is + begin + This.Counter := UInt32 (Value); + end Set_Counter; + + ----------------- + -- Set_Counter -- + ----------------- + + procedure Set_Counter (This : in out Timer; Value : UInt32) is + begin + This.Counter := Value; + end Set_Counter; + + --------------------- + -- Current_Counter -- + --------------------- + + function Current_Counter (This : Timer) return UInt32 is + begin + return This.Counter; + end Current_Counter; + + -------------------- + -- Set_Autoreload -- + -------------------- + + procedure Set_Autoreload (This : in out Timer; Value : UInt32) is + begin + This.ARR := Value; + end Set_Autoreload; + + ------------------------ + -- Current_Autoreload -- + ------------------------ + + function Current_Autoreload (This : Timer) return UInt32 is + begin + return This.ARR; + end Current_Autoreload; + + ---------------------- + -- Enable_Interrupt -- + ---------------------- + + procedure Enable_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + is + begin + This.DIER := This.DIER or Source'Enum_Rep; + end Enable_Interrupt; + + ---------------------- + -- Enable_Interrupt -- + ---------------------- + + procedure Enable_Interrupt + (This : in out Timer; + Sources : Timer_Interrupt_List) + is + begin + for Source of Sources loop + This.DIER := This.DIER or Source'Enum_Rep; + end loop; + end Enable_Interrupt; + + ----------------------- + -- Disable_Interrupt -- + ----------------------- + + procedure Disable_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + is + begin + This.DIER := This.DIER and not Source'Enum_Rep; + end Disable_Interrupt; + + ----------------------------- + -- Clear_Pending_Interrupt -- + ----------------------------- + + procedure Clear_Pending_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + is + begin + This.SR := not Source'Enum_Rep; + -- We do not, and must not, use the read-modify-write pattern because + -- it leaves a window of vulnerability open to changes to the state + -- after the read but before the write. The hardware for this register + -- is designed so that writing other bits will not change them. This is + -- indicated by the "rc_w0" notation in the status register definition. + -- See the RM, page 57 for that notation explanation. + end Clear_Pending_Interrupt; + + ----------------------- + -- Interrupt_Enabled -- + ----------------------- + + function Interrupt_Enabled + (This : Timer; + Source : Timer_Interrupt) + return Boolean + is + begin + return (This.DIER and Source'Enum_Rep) = Source'Enum_Rep; + end Interrupt_Enabled; + + ------------ + -- Status -- + ------------ + + function Status (This : Timer; Flag : Timer_Status_Flag) return Boolean is + begin + return (This.SR and Flag'Enum_Rep) = Flag'Enum_Rep; + end Status; + + ------------------ + -- Clear_Status -- + ------------------ + + procedure Clear_Status (This : in out Timer; Flag : Timer_Status_Flag) is + begin + This.SR := not Flag'Enum_Rep; + -- We do not, and must not, use the read-modify-write pattern because + -- it leaves a window of vulnerability open to changes to the state + -- after the read but before the write. The hardware for this register + -- is designed so that writing other bits will not change them. This is + -- indicated by the "rc_w0" notation in the status register definition. + -- See the RM, page 57 for that notation explanation. + end Clear_Status; + + ----------------------- + -- Enable_DMA_Source -- + ----------------------- + + procedure Enable_DMA_Source + (This : in out Timer; + Source : Timer_DMA_Source) + is + begin + This.DIER := This.DIER or Source'Enum_Rep; + end Enable_DMA_Source; + + ------------------------ + -- Disable_DMA_Source -- + ------------------------ + + procedure Disable_DMA_Source + (This : in out Timer; + Source : Timer_DMA_Source) + is + begin + This.DIER := This.DIER and not Source'Enum_Rep; + end Disable_DMA_Source; + + ------------------------ + -- DMA_Source_Enabled -- + ------------------------ + + function DMA_Source_Enabled + (This : Timer; + Source : Timer_DMA_Source) + return Boolean + is + begin + return (This.DIER and Source'Enum_Rep) = Source'Enum_Rep; + end DMA_Source_Enabled; + + ------------------------- + -- Configure_Prescaler -- + ------------------------- + + procedure Configure_Prescaler + (This : in out Timer; + Prescaler : UInt16; + Reload_Mode : Timer_Prescaler_Reload_Mode) + is + begin + This.Prescaler := Prescaler; + This.EGR := Reload_Mode'Enum_Rep; + end Configure_Prescaler; + + ------------------- + -- Configure_DMA -- + ------------------- + + procedure Configure_DMA + (This : in out Timer; + Base_Address : Timer_DMA_Base_Address; + Burst_Length : Timer_DMA_Burst_Length) + is + begin + This.DCR.Base_Address := Base_Address; + This.DCR.Burst_Length := Burst_Length; + end Configure_DMA; + + -------------------------------- + -- Enable_Capture_Compare_DMA -- + -------------------------------- + + procedure Enable_Capture_Compare_DMA + (This : in out Timer) + -- TODO: note that the CCDS field description in the RM, page 550, seems + -- to indicate other than simply enabled/disabled + is + begin + This.CR2.Capture_Compare_DMA_Selection := True; + end Enable_Capture_Compare_DMA; + + --------------------------------- + -- Disable_Capture_Compare_DMA -- + --------------------------------- + + procedure Disable_Capture_Compare_DMA + (This : in out Timer) + -- TODO: note that the CCDS field description in the RM, page 550, seems + -- to indicate other than simply enabled/disabled + is + begin + This.CR2.Capture_Compare_DMA_Selection := False; + end Disable_Capture_Compare_DMA; + + ----------------------- + -- Current_Prescaler -- + ----------------------- + + function Current_Prescaler (This : Timer) return UInt16 is + begin + return This.Prescaler; + end Current_Prescaler; + + ----------------------- + -- Set_UpdateDisable -- + ----------------------- + + procedure Set_UpdateDisable + (This : in out Timer; + To : Boolean) + is + begin + This.CR1.Update_Disable := To; + end Set_UpdateDisable; + + ----------------------- + -- Set_UpdateRequest -- + ----------------------- + + procedure Set_UpdateRequest + (This : in out Timer; + Source : Timer_Update_Source) + is + begin + This.CR1.Update_Request_Source := Source /= Global; + end Set_UpdateRequest; + + --------------------------- + -- Select_One_Pulse_Mode -- + --------------------------- + + procedure Select_One_Pulse_Mode + (This : in out Timer; + Mode : Timer_One_Pulse_Mode) + is + begin + This.CR1.One_Pulse_Mode := Mode; + end Select_One_Pulse_Mode; + + ---------------------------- + -- Set_Autoreload_Preload -- + ---------------------------- + + procedure Set_Autoreload_Preload + (This : in out Timer; + To : Boolean) + is + begin + This.CR1.ARPE := To; + end Set_Autoreload_Preload; + + ----------------------- + -- Counter_Direction -- + ----------------------- + + function Current_Counter_Mode + (This : Timer) + return Timer_Counter_Alignment_Mode + is + begin + if Basic_Timer (This) then + return Up; + else + return This.CR1.Mode_And_Dir; + end if; + end Current_Counter_Mode; + + -------------------- + -- Generate_Event -- + -------------------- + + procedure Generate_Event + (This : in out Timer; + Source : Timer_Event_Source) + is + Temp_EGR : UInt32 := This.EGR; + begin + Temp_EGR := Temp_EGR or Source'Enum_Rep; + This.EGR := Temp_EGR; + end Generate_Event; + + --------------------------- + -- Select_Output_Trigger -- + --------------------------- + + procedure Select_Output_Trigger + (This : in out Timer; + Source : Timer_Trigger_Output_Source) + is + begin + This.CR2.Master_Mode_Selection := Source; + end Select_Output_Trigger; + + ----------------------- + -- Select_Slave_Mode -- + ----------------------- + + procedure Select_Slave_Mode + (This : in out Timer; + Mode : Timer_Slave_Mode) + is + begin + This.SMCR.Slave_Mode_Selection := Mode; + end Select_Slave_Mode; + + ------------------------------ + -- Enable_Master_Slave_Mode -- + ------------------------------ + + procedure Enable_Master_Slave_Mode (This : in out Timer) is + begin + This.SMCR.Master_Slave_Mode := True; + end Enable_Master_Slave_Mode; + + ------------------------------- + -- Disable_Master_Slave_Mode -- + ------------------------------- + + procedure Disable_Master_Slave_Mode (This : in out Timer) is + begin + This.SMCR.Master_Slave_Mode := False; + end Disable_Master_Slave_Mode; + + -------------------------------- + -- Configure_External_Trigger -- + -------------------------------- + + procedure Configure_External_Trigger + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + is + begin + This.SMCR.External_Trigger_Polarity := Polarity; + This.SMCR.External_Trigger_Prescaler := Prescaler; + This.SMCR.External_Trigger_Filter := Filter; + end Configure_External_Trigger; + + --------------------------------- + -- Configure_As_External_Clock -- + --------------------------------- + + procedure Configure_As_External_Clock + (This : in out Timer; + Source : Timer_Internal_Trigger_Source) + is + begin + Select_Input_Trigger (This, Source); + Select_Slave_Mode (This, External_1); + end Configure_As_External_Clock; + + --------------------------------- + -- Configure_As_External_Clock -- + --------------------------------- + + procedure Configure_As_External_Clock + (This : in out Timer; + Source : Timer_External_Clock_Source; + Polarity : Timer_Input_Capture_Polarity; + Filter : Timer_Input_Capture_Filter) + is + begin + if Source = Filtered_Timer_Input_2 then + Configure_Channel_Input + (This, + Channel_2, + Polarity, + Direct_TI, + Div1, -- default prescalar zero value + Filter); + else + Configure_Channel_Input + (This, + Channel_1, + Polarity, + Direct_TI, + Div1, -- default prescalar zero value + Filter); + end if; + Select_Input_Trigger (This, Source); + Select_Slave_Mode (This, External_1); + end Configure_As_External_Clock; + + ------------------------------------ + -- Configure_External_Clock_Mode1 -- + ------------------------------------ + + procedure Configure_External_Clock_Mode1 + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + is + begin + Configure_External_Trigger (This, Polarity, Prescaler, Filter); + Select_Slave_Mode (This, External_1); + Select_Input_Trigger (This, External_Trigger_Input); + end Configure_External_Clock_Mode1; + + ------------------------------------ + -- Configure_External_Clock_Mode2 -- + ------------------------------------ + + procedure Configure_External_Clock_Mode2 + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + is + begin + Configure_External_Trigger (This, Polarity, Prescaler, Filter); + This.SMCR.External_Clock_Enable := True; + end Configure_External_Clock_Mode2; + + -------------------------- + -- Select_Input_Trigger -- + -------------------------- + + procedure Select_Input_Trigger + (This : in out Timer; + Source : Timer_Trigger_Input_Source) + is + begin + This.SMCR.Trigger_Selection := Source; + end Select_Input_Trigger; + + ------------------------------ + -- Configure_Channel_Output -- + ------------------------------ + + procedure Configure_Channel_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + State : Timer_Capture_Compare_State; + Pulse : UInt32; + Polarity : Timer_Output_Compare_Polarity) + is + begin + -- first disable the channel + This.CCER (Channel).CCxE := Disable; + + Set_Output_Compare_Mode (This, Channel, Mode); + + This.CCER (Channel).CCxE := State; + This.CCER (Channel).CCxP := Polarity'Enum_Rep; + + This.CCR1_4 (Channel) := Pulse; + -- Only timers 2 and 5 have 32-bit CCR registers. The others must + -- maintain the upper half at zero. We use a precondition to ensure + -- values greater than a half-word are only specified for the proper + -- timers. + end Configure_Channel_Output; + + ------------------------------ + -- Configure_Channel_Output -- + ------------------------------ + + procedure Configure_Channel_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + State : Timer_Capture_Compare_State; + Pulse : UInt32; + Polarity : Timer_Output_Compare_Polarity; + Idle_State : Timer_Capture_Compare_State; + Complementary_Polarity : Timer_Output_Compare_Polarity; + Complementary_Idle_State : Timer_Capture_Compare_State) + is + begin + -- first disable the channel + This.CCER (Channel).CCxE := Disable; + + Set_Output_Compare_Mode (This, Channel, Mode); + + This.CCER (Channel).CCxE := State; + This.CCER (Channel).CCxNP := Complementary_Polarity'Enum_Rep; + This.CCER (Channel).CCxP := Polarity'Enum_Rep; + + case Channel is + when Channel_1 => + This.CR2.Channel_1_Output_Idle_State := Idle_State; + This.CR2.Channel_1_Complementary_Output_Idle_State := + Complementary_Idle_State; + when Channel_2 => + This.CR2.Channel_2_Output_Idle_State := Idle_State; + This.CR2.Channel_2_Complementary_Output_Idle_State := + Complementary_Idle_State; + when Channel_3 => + This.CR2.Channel_3_Output_Idle_State := Idle_State; + This.CR2.Channel_3_Complementary_Output_Idle_State := + Complementary_Idle_State; + when Channel_4 => + This.CR2.Channel_4_Output_Idle_State := Idle_State; + end case; + + This.CCR1_4 (Channel) := Pulse; + -- Only timers 2 and 5 have 32-bit CCR registers. The others must + -- maintain the upper half at zero. We use a precondition to ensure + -- values greater than a half-word are only specified for the proper + -- timers. + end Configure_Channel_Output; + + ----------------------- + -- Set_Single_Output -- + ----------------------- + + procedure Set_Single_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + OC_Clear_Enabled : Boolean; + Preload_Enabled : Boolean; + Fast_Enabled : Boolean) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + Description : Channel_Output_Descriptor; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + Description := (OCxMode => Mode, + OCxFast_Enable => Fast_Enabled, + OCxPreload_Enable => Preload_Enabled, + OCxClear_Enable => OC_Clear_Enabled); + + Temp.Descriptors (Descriptor_Index) := (Output, Description); + + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Single_Output; + + ----------------------------- + -- Set_Output_Compare_Mode -- + ----------------------------- + + procedure Set_Output_Compare_Mode + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + if Temp.Descriptors (Descriptor_Index).CCxSelection /= Output then + raise Timer_Channel_Access_Error; + end if; + + Temp.Descriptors (Descriptor_Index).Compare.OCxMode := Mode; + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Output_Compare_Mode; + + ---------------------------------- + -- Current_Capture_Compare_Mode -- + ---------------------------------- + + function Current_Capture_Compare_Mode + (This : Timer; + Channel : Timer_Channel) + return Timer_Capture_Compare_Modes + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + return Temp.Descriptors (Descriptor_Index).CCxSelection; + end Current_Capture_Compare_Mode; + + ------------------------------ + -- Set_Output_Forced_Action -- + ------------------------------ + + procedure Set_Output_Forced_Action + (This : in out Timer; + Channel : Timer_Channel; + Active : Boolean) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + if Temp.Descriptors (Descriptor_Index).CCxSelection /= Output then + raise Timer_Channel_Access_Error; + end if; + + if Active then + Temp.Descriptors (Descriptor_Index).Compare.OCxMode := Force_Active; + else + Temp.Descriptors (Descriptor_Index).Compare.OCxMode := Force_Inactive; + end if; + + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Output_Forced_Action; + + ------------------------------- + -- Set_Output_Preload_Enable -- + ------------------------------- + + procedure Set_Output_Preload_Enable + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + Temp.Descriptors (Descriptor_Index).Compare.OCxPreload_Enable := Enabled; + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Output_Preload_Enable; + + ---------------------------- + -- Set_Output_Fast_Enable -- + ---------------------------- + + procedure Set_Output_Fast_Enable + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + Temp.Descriptors (Descriptor_Index).Compare.OCxFast_Enable := Enabled; + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Output_Fast_Enable; + + ----------------------- + -- Set_Clear_Control -- + ----------------------- + + procedure Set_Clear_Control + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + Temp.Descriptors (Descriptor_Index).Compare.OCxClear_Enable := Enabled; + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Clear_Control; + + -------------------- + -- Enable_Channel -- + -------------------- + + procedure Enable_Channel + (This : in out Timer; + Channel : Timer_Channel) + is + Temp_EGR : UInt32 := This.EGR; + begin + This.CCER (Channel).CCxE := Enable; + + -- Trigger an event to initialize preload register + Temp_EGR := Temp_EGR or (2 ** (Timer_Channel'Pos (Channel) + 1)); + + This.EGR := Temp_EGR; + end Enable_Channel; + + ------------------------- + -- Set_Output_Polarity -- + ------------------------- + + procedure Set_Output_Polarity + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Output_Compare_Polarity) + is + begin + This.CCER (Channel).CCxP := Polarity'Enum_Rep; + end Set_Output_Polarity; + + --------------------------------------- + -- Set_Output_Complementary_Polarity -- + --------------------------------------- + + procedure Set_Output_Complementary_Polarity + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Output_Compare_Polarity) + is + begin + This.CCER (Channel).CCxNP := Polarity'Enum_Rep; + end Set_Output_Complementary_Polarity; + + --------------------- + -- Disable_Channel -- + --------------------- + + procedure Disable_Channel + (This : in out Timer; + Channel : Timer_Channel) + is + begin + This.CCER (Channel).CCxE := Disable; + end Disable_Channel; + + --------------------- + -- Channel_Enabled -- + --------------------- + + function Channel_Enabled + (This : Timer; + Channel : Timer_Channel) + return Boolean + is + begin + return This.CCER (Channel).CCxE = Enable; + end Channel_Enabled; + + ---------------------------------- + -- Enable_Complementary_Channel -- + ---------------------------------- + + procedure Enable_Complementary_Channel + (This : in out Timer; + Channel : Timer_Channel) + is + begin + This.CCER (Channel).CCxNE := Enable; + end Enable_Complementary_Channel; + + ----------------------------------- + -- Disable_Complementary_Channel -- + ----------------------------------- + + procedure Disable_Complementary_Channel + (This : in out Timer; + Channel : Timer_Channel) + is + begin + This.CCER (Channel).CCxNE := Disable; + end Disable_Complementary_Channel; + + ----------------------------------- + -- Complementary_Channel_Enabled -- + ----------------------------------- + + function Complementary_Channel_Enabled + (This : Timer; Channel : Timer_Channel) + return Boolean + is + begin + return This.CCER (Channel).CCxNE = Enable; + end Complementary_Channel_Enabled; + + ----------------------- + -- Set_Compare_Value -- + ----------------------- + + procedure Set_Compare_Value + (This : in out Timer; + Channel : Timer_Channel; + Word_Value : UInt32) + is + begin + This.CCR1_4 (Channel) := Word_Value; + -- Timers 2 and 5 really do have 32-bit capture/compare registers so we + -- don't need to require half-words as inputs. + end Set_Compare_Value; + + ----------------------- + -- Set_Compare_Value -- + ----------------------- + + procedure Set_Compare_Value + (This : in out Timer; + Channel : Timer_Channel; + Value : UInt16) + is + begin + This.CCR1_4 (Channel) := UInt32 (Value); + -- These capture/compare registers are really only 15-bits wide, except + -- for those of timers 2 and 5. For the sake of simplicity we represent + -- all of them with full words, but only write word values when + -- appropriate. The caller has to treat them as half-word values, since + -- that's the type for the formal parameter, therefore our casting up to + -- a word value will retain the reserved upper half-word value of zero. + end Set_Compare_Value; + + --------------------------- + -- Current_Capture_Value -- + --------------------------- + + function Current_Capture_Value + (This : Timer; + Channel : Timer_Channel) + return UInt32 + is + begin + return This.CCR1_4 (Channel); + end Current_Capture_Value; + + --------------------------- + -- Current_Capture_Value -- + --------------------------- + + function Current_Capture_Value + (This : Timer; + Channel : Timer_Channel) + return UInt16 + is + begin + return UInt16 (This.CCR1_4 (Channel)); + end Current_Capture_Value; + + ------------------------------------- + -- Write_Channel_Input_Description -- + ------------------------------------- + + procedure Write_Channel_Input_Description + (This : in out Timer; + Channel : Timer_Channel; + Kind : Timer_Input_Capture_Selection; + Description : Channel_Input_Descriptor) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + New_Value : IO_Descriptor; + begin + case Kind is + when Direct_TI => + New_Value := (CCxSelection => Direct_TI, Capture => Description); + when Indirect_TI => + New_Value := (CCxSelection => Indirect_TI, Capture => Description); + when TRC => + New_Value := (CCxSelection => TRC, Capture => Description); + end case; + + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + Temp.Descriptors (Descriptor_Index) := New_Value; + This.CCMR1_2 (CCMR_Index) := Temp; + end Write_Channel_Input_Description; + + ------------------------- + -- Set_Input_Prescaler -- + ------------------------- + + procedure Set_Input_Prescaler + (This : in out Timer; + Channel : Timer_Channel; + Value : Timer_Input_Capture_Prescaler) + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + Temp.Descriptors (Descriptor_Index).Capture.ICxPrescaler := Value; + This.CCMR1_2 (CCMR_Index) := Temp; + end Set_Input_Prescaler; + + ----------------------------- + -- Current_Input_Prescaler -- + ----------------------------- + + function Current_Input_Prescaler + (This : Timer; + Channel : Timer_Channel) + return Timer_Input_Capture_Prescaler + is + CCMR_Index : CCMRx_Index; + Descriptor_Index : Lower_Half_Index; + Temp : TIMx_CCMRx; + begin + case Channel is + when Channel_1 => + CCMR_Index := 1; + Descriptor_Index := 1; + when Channel_2 => + CCMR_Index := 1; + Descriptor_Index := 2; + when Channel_3 => + CCMR_Index := 2; + Descriptor_Index := 1; + when Channel_4 => + CCMR_Index := 2; + Descriptor_Index := 2; + end case; + Temp := This.CCMR1_2 (CCMR_Index); -- effectively get CCMR1 or CCMR2 + + return Temp.Descriptors (Descriptor_Index).Capture.ICxPrescaler; + end Current_Input_Prescaler; + + ----------------------------- + -- Configure_Channel_Input -- + ----------------------------- + + procedure Configure_Channel_Input + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Input_Capture_Polarity; + Selection : Timer_Input_Capture_Selection; + Prescaler : Timer_Input_Capture_Prescaler; + Filter : Timer_Input_Capture_Filter) + is + Input : Channel_Input_Descriptor; + begin + -- first disable the channel + This.CCER (Channel).CCxE := Disable; + + Input := (ICxFilter => Filter, ICxPrescaler => Prescaler); + Write_Channel_Input_Description + (This => This, + Channel => Channel, + Kind => Selection, + Description => Input); + + case Polarity is + when Rising => + This.CCER (Channel).CCxNP := 0; + This.CCER (Channel).CCxP := 0; + when Falling => + This.CCER (Channel).CCxNP := 0; + This.CCER (Channel).CCxP := 1; + when Both_Edges => + This.CCER (Channel).CCxNP := 1; + This.CCER (Channel).CCxP := 1; + end case; + + This.CCER (Channel).CCxE := Enable; + end Configure_Channel_Input; + + --------------------------------- + -- Configure_Channel_Input_PWM -- + --------------------------------- + + procedure Configure_Channel_Input_PWM + (This : in out Timer; + Channel : Timer_Channel; + Selection : Timer_Input_Capture_Selection; + Polarity : Timer_Input_Capture_Polarity; + Prescaler : Timer_Input_Capture_Prescaler; + Filter : Timer_Input_Capture_Filter) + is + Opposite_Polarity : Timer_Input_Capture_Polarity; + Opposite_Selection : Timer_Input_Capture_Selection; + begin + Disable_Channel (This, Channel); + + if Polarity = Rising then + Opposite_Polarity := Falling; + else + Opposite_Polarity := Rising; + end if; + + if Selection = Indirect_TI then + Opposite_Selection := Direct_TI; + else + Opposite_Selection := Indirect_TI; + end if; + + if Channel = Channel_1 then + Configure_Channel_Input + (This, Channel_1, Polarity, Selection, Prescaler, Filter); + + Configure_Channel_Input (This, + Channel_2, + Opposite_Polarity, + Opposite_Selection, + Prescaler, + Filter); + else + Configure_Channel_Input + (This, Channel_2, Polarity, Selection, Prescaler, Filter); + + Configure_Channel_Input (This, + Channel_1, + Opposite_Polarity, + Opposite_Selection, + Prescaler, + Filter); + end if; + + Enable_Channel (This, Channel); + end Configure_Channel_Input_PWM; + + ------------------------------- + -- Enable_CC_Preload_Control -- + ------------------------------- + + procedure Enable_CC_Preload_Control (This : in out Timer) is + begin + This.CR2.Capture_Compare_Preloaded_Control := True; + end Enable_CC_Preload_Control; + + -------------------------------- + -- Disable_CC_Preload_Control -- + -------------------------------- + + procedure Disable_CC_Preload_Control (This : in out Timer) is + begin + This.CR2.Capture_Compare_Preloaded_Control := False; + end Disable_CC_Preload_Control; + + ------------------------ + -- Select_Commutation -- + ------------------------ + + procedure Select_Commutation (This : in out Timer) is + begin + This.CR2.Capture_Compare_Control_Update_Selection := True; + end Select_Commutation; + + -------------------------- + -- Deselect_Commutation -- + -------------------------- + + procedure Deselect_Commutation (This : in out Timer) is + begin + This.CR2.Capture_Compare_Control_Update_Selection := False; + end Deselect_Commutation; + + -------------------- + -- Configure_BDTR -- + -------------------- + + procedure Configure_BDTR + (This : in out Timer; + Automatic_Output_Enabled : Boolean; + Break_Polarity : Timer_Break_Polarity; + Break_Enabled : Boolean; + Off_State_Selection_Run_Mode : Bit; + Off_State_Selection_Idle_Mode : Bit; + Lock_Configuration : Timer_Lock_Level; + Deadtime_Generator : UInt8) + is + begin + This.BDTR.Automatic_Output_Enabled := Automatic_Output_Enabled; + This.BDTR.Break_Polarity := Break_Polarity; + This.BDTR.Break_Enable := Break_Enabled; + This.BDTR.Off_State_Selection_Run_Mode := Off_State_Selection_Run_Mode; + This.BDTR.Off_State_Selection_Idle_Mode := Off_State_Selection_Idle_Mode; + This.BDTR.Lock := Lock_Configuration; + This.BDTR.Deadtime_Generator := Deadtime_Generator; + end Configure_BDTR; + + --------------------------------- + -- Configure_Timer_2_Remapping -- + --------------------------------- + + procedure Configure_Timer_2_Remapping + (This : in out Timer; + Option : Timer_2_Remapping_Options) + is + begin + This.Options.ITR1_RMP := Option; + end Configure_Timer_2_Remapping; + + --------------------------------- + -- Configure_Timer_5_Remapping -- + --------------------------------- + + procedure Configure_Timer_5_Remapping + (This : in out Timer; + Option : Timer_5_Remapping_Options) + is + begin + This.Options.TI4_RMP := Option; + end Configure_Timer_5_Remapping; + + ---------------------------------- + -- Configure_Timer_11_Remapping -- + ---------------------------------- + + procedure Configure_Timer_11_Remapping + (This : in out Timer; + Option : Timer_11_Remapping_Options) + is + begin + This.Options.TI1_RMP := Option; + end Configure_Timer_11_Remapping; + + --------------------------------- + -- Configure_Encoder_Interface -- + --------------------------------- + + procedure Configure_Encoder_Interface + (This : in out Timer; + Mode : Timer_Encoder_Mode; + IC1_Polarity : Timer_Input_Capture_Polarity; + IC2_Polarity : Timer_Input_Capture_Polarity) + is + begin + This.SMCR.Slave_Mode_Selection := Mode; + + Write_Channel_Input_Description + (This, + Channel => Channel_1, + Kind => Direct_TI, + Description => Channel_Input_Descriptor'(ICxFilter => 0, + ICxPrescaler => Div1)); + + Write_Channel_Input_Description + (This, + Channel => Channel_2, + Kind => Direct_TI, + Description => Channel_Input_Descriptor'(ICxFilter => 0, + ICxPrescaler => Div1)); + + case IC1_Polarity is + when Rising => + This.CCER (Channel_1).CCxNP := 0; + This.CCER (Channel_1).CCxP := 0; + when Falling => + This.CCER (Channel_1).CCxNP := 0; + This.CCER (Channel_1).CCxP := 1; + when Both_Edges => + This.CCER (Channel_1).CCxNP := 1; + This.CCER (Channel_1).CCxP := 1; + end case; + + case IC2_Polarity is + when Rising => + This.CCER (Channel_2).CCxNP := 0; + This.CCER (Channel_2).CCxP := 0; + when Falling => + This.CCER (Channel_2).CCxNP := 0; + This.CCER (Channel_2).CCxP := 1; + when Both_Edges => + This.CCER (Channel_2).CCxNP := 1; + This.CCER (Channel_2).CCxP := 1; + end case; + end Configure_Encoder_Interface; + + ------------------------ + -- Enable_Hall_Sensor -- + ------------------------ + + procedure Enable_Hall_Sensor + (This : in out Timer) + is + begin + This.CR2.TI1_Selection := True; + end Enable_Hall_Sensor; + + ------------------------- + -- Disable_Hall_Sensor -- + ------------------------- + + procedure Disable_Hall_Sensor + (This : in out Timer) + is + begin + This.CR2.TI1_Selection := False; + end Disable_Hall_Sensor; + +end STM32.Timers; diff --git a/arch/ARM/STM32/devices/stm32f401/stm32-timers.ads b/arch/ARM/STM32/devices/stm32f401/stm32-timers.ads new file mode 100644 index 000000000..8d811443e --- /dev/null +++ b/arch/ARM/STM32/devices/stm32f401/stm32-timers.ads @@ -0,0 +1,1500 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_tim.h -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief Header file of timers HAL module. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides definitions for the timers on the STM32F411 (ARM Cortex +-- M4F) microcontrollers from ST Microelectronics. + +pragma Restrictions (No_Elaboration_Code); + +with System; use System; +with STM32_SVD; + +package STM32.Timers is + + type Timer is limited private; + + procedure Enable (This : in out Timer) + with Post => Enabled (This); + + procedure Disable (This : in out Timer) + with Post => (if No_Outputs_Enabled (This) then not Enabled (This)); + + function Enabled (This : Timer) return Boolean; + + -- The Configure routines are overloaded for the sake of + -- additional timer-class specific parameters. + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32) + with + Pre => (if Period > UInt32 (UInt16'Last) then Has_32bit_Counter (This)), + Post => Current_Prescaler (This) = Prescaler and + Current_Autoreload (This) = Period; + + procedure Set_Counter (This : in out Timer; Value : UInt16) + with Post => Current_Counter (This) = UInt32 (Value); + + procedure Set_Counter (This : in out Timer; Value : UInt32) + with + Pre => Has_32bit_Counter (This), + Post => Current_Counter (This) = Value; + + function Current_Counter (This : Timer) return UInt32; + -- For those timers that actually have a 32-bit counter this function will + -- return the full word value. For the other timers, the upper half-word of + -- the result will be all zeros so in effect the result will be a half-word + -- value. + + procedure Set_Autoreload (This : in out Timer; Value : UInt32) + with + Pre => (if Value > UInt32 (UInt16'Last) then Has_32bit_Counter (This)), + Post => Current_Autoreload (This) = Value; + + function Current_Autoreload (This : Timer) return UInt32; + -- Returns the value of the timer's Auto Reload Register (ARR) + + type Timer_Clock_Divisor is (Div1, Div2, Div4); + + procedure Set_Clock_Division + (This : in out Timer; + Value : Timer_Clock_Divisor) + with + Pre => not Basic_Timer (This), + Post => Current_Clock_Division (This) = Value; + + function Current_Clock_Division (This : Timer) return Timer_Clock_Divisor; + + type Timer_Counter_Alignment_Mode is + (Up, Down, Center_Aligned1, Center_Aligned2, Center_Aligned3); + -- We combine the up-down direction and the center-aligned mode selection + -- into a single type because the two are interdependent and we don't want + -- the user to have to remember to set the direction when not using one + -- of the center-aligned choices. The discontiguous binary values used to + -- represent the enumerals reflect the combination of the adjacent fields + -- within the timer representation. + + for Timer_Counter_Alignment_Mode use + (Up => 2#000#, + Down => 2#001#, + Center_Aligned1 => 2#010#, + Center_Aligned2 => 2#100#, + Center_Aligned3 => 2#110#); + + procedure Set_Counter_Mode + (This : in out Timer; + Value : Timer_Counter_Alignment_Mode) + with Post => Current_Counter_Mode (This) = Value; + + function Current_Counter_Mode + (This : Timer) + return Timer_Counter_Alignment_Mode; + -- Note that the basic timers only count up. + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32; + Clock_Divisor : Timer_Clock_Divisor; + Counter_Mode : Timer_Counter_Alignment_Mode) + with + Pre => not Basic_Timer (This) and + (if Period > UInt32 (UInt16'Last) then Has_32bit_Counter (This)), + Post => Current_Prescaler (This) = Prescaler and + Current_Clock_Division (This) = Clock_Divisor and + Current_Counter_Mode (This) = Counter_Mode and + Current_Autoreload (This) = Period; + + type Timer_Prescaler_Reload_Mode is (Update, Immediate); + + procedure Configure_Prescaler + (This : in out Timer; + Prescaler : UInt16; + Reload_Mode : Timer_Prescaler_Reload_Mode) + with Post => Current_Prescaler (This) = Prescaler; + + function Current_Prescaler (This : Timer) return UInt16; + + procedure Set_UpdateDisable + (This : in out Timer; + To : Boolean); + + type Timer_Update_Source is (Global, Regular); + + procedure Set_UpdateRequest + (This : in out Timer; + Source : Timer_Update_Source); + + procedure Set_Autoreload_Preload + (This : in out Timer; + To : Boolean); + + type Timer_One_Pulse_Mode is (Repetitive, Single); + + procedure Select_One_Pulse_Mode + (This : in out Timer; + Mode : Timer_One_Pulse_Mode) + with Post => (if Mode = Single then not Enabled (This)); + + ---------------------------------------------------------------------------- + + -- Interrupts, DMA, Flags Management -------------------------------------- + + ---------------------------------------------------------------------------- + + type Timer_Interrupt is + (Timer_Update_Interrupt, + Timer_CC1_Interrupt, + Timer_CC2_Interrupt, + Timer_CC3_Interrupt, + Timer_CC4_Interrupt, + Timer_COM_Interrupt, + Timer_Trigger_Interrupt, + Timer_Break_Interrupt); + + for Timer_Interrupt use + (Timer_Update_Interrupt => 2#00000001#, + Timer_CC1_Interrupt => 2#00000010#, + Timer_CC2_Interrupt => 2#00000100#, + Timer_CC3_Interrupt => 2#00001000#, + Timer_CC4_Interrupt => 2#00010000#, + Timer_COM_Interrupt => 2#00100000#, + Timer_Trigger_Interrupt => 2#01000000#, + Timer_Break_Interrupt => 2#10000000#); + + procedure Enable_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + with + Pre => + (if Basic_Timer (This) then Source = Timer_Update_Interrupt) and + (if Source in Timer_COM_Interrupt | Timer_Break_Interrupt + then Advanced_Timer (This)), + Post => Interrupt_Enabled (This, Source); + + type Timer_Interrupt_List is array (Positive range <>) of Timer_Interrupt; + + procedure Enable_Interrupt + (This : in out Timer; + Sources : Timer_Interrupt_List) + with + Pre => + (for all Source of Sources => + (if Basic_Timer (This) then Source = Timer_Update_Interrupt) and + (if Source in Timer_COM_Interrupt | Timer_Break_Interrupt + then Advanced_Timer (This))), + Post => (for all Source of Sources => Interrupt_Enabled (This, Source)); + + procedure Disable_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + with + Pre => + (if Basic_Timer (This) then Source = Timer_Update_Interrupt) and + (if Source in Timer_COM_Interrupt | Timer_Break_Interrupt + then Advanced_Timer (This)), + Post => not Interrupt_Enabled (This, Source); + + procedure Clear_Pending_Interrupt + (This : in out Timer; + Source : Timer_Interrupt) + with Pre => + (if Basic_Timer (This) then Source = Timer_Update_Interrupt) and + (if Source in Timer_COM_Interrupt | Timer_Break_Interrupt + then Advanced_Timer (This)); + + function Interrupt_Enabled + (This : Timer; + Source : Timer_Interrupt) + return Boolean + with Pre => + (if Basic_Timer (This) then Source = Timer_Update_Interrupt) and + (if Source in Timer_COM_Interrupt | Timer_Break_Interrupt + then Advanced_Timer (This)); + + type Timer_Event_Source is + (Event_Source_Update, + Event_Source_CC1, + Event_Source_CC2, + Event_Source_CC3, + Event_Source_CC4, + Event_Source_COM, + Event_Source_Trigger, + Event_Source_Break); + + for Timer_Event_Source use + (Event_Source_Update => 16#0001#, + Event_Source_CC1 => 16#0002#, + Event_Source_CC2 => 16#0004#, + Event_Source_CC3 => 16#0008#, + Event_Source_CC4 => 16#0010#, + Event_Source_COM => 16#0020#, + Event_Source_Trigger => 16#0040#, + Event_Source_Break => 16#0080#); + -- TODO: consider alternative to bit-masks + + procedure Generate_Event + (This : in out Timer; + Source : Timer_Event_Source) + with + Pre => + (if Basic_Timer (This) then Source = Event_Source_Update) and + (if Source in Event_Source_COM | Event_Source_Break + then Advanced_Timer (This)); + + type Timer_Status_Flag is + (Timer_Update_Indicated, + Timer_CC1_Indicated, + Timer_CC2_Indicated, + Timer_CC3_Indicated, + Timer_CC4_Indicated, + Timer_COM_Indicated, + Timer_Trigger_Indicated, + Timer_Break_Indicated, + Timer_CC1OF_Indicated, + Timer_CC2OF_Indicated, + Timer_CC3OF_Indicated, + Timer_CC4OF_Indicated); + + for Timer_Status_Flag use + (Timer_Update_Indicated => 2#000000000001#, + Timer_CC1_Indicated => 2#000000000010#, + Timer_CC2_Indicated => 2#000000000100#, + Timer_CC3_Indicated => 2#000000001000#, + Timer_CC4_Indicated => 2#000000010000#, + Timer_COM_Indicated => 2#000000100000#, + Timer_Trigger_Indicated => 2#000001000000#, + Timer_Break_Indicated => 2#000010000000#, + Timer_CC1OF_Indicated => 2#000100000000#, + Timer_CC2OF_Indicated => 2#001000000000#, + Timer_CC3OF_Indicated => 2#010000000000#, + Timer_CC4OF_Indicated => 2#100000000000#); + + function Status + (This : Timer; + Flag : Timer_Status_Flag) + return Boolean + with Pre => + (if Basic_Timer (This) then Flag = Timer_Update_Indicated) and + (if Flag in Timer_COM_Indicated | Timer_Break_Indicated + then Advanced_Timer (This)); + + procedure Clear_Status + (This : in out Timer; + Flag : Timer_Status_Flag) + with + Pre => + (if Basic_Timer (This) then Flag = Timer_Update_Indicated) and + (if Flag in Timer_COM_Indicated | Timer_Break_Indicated + then Advanced_Timer (This)), + Post => + not Status (This, Flag); + + type Timer_DMA_Source is + (Timer_DMA_Update, + Timer_DMA_CC1, + Timer_DMA_CC2, + Timer_DMA_CC3, + Timer_DMA_CC4, + Timer_DMA_COM, + Timer_DMA_Trigger); + + for Timer_DMA_Source use + (Timer_DMA_Update => 2#00000001_00000000#, + Timer_DMA_CC1 => 2#00000010_00000000#, + Timer_DMA_CC2 => 2#00000100_00000000#, + Timer_DMA_CC3 => 2#00001000_00000000#, + Timer_DMA_CC4 => 2#00010000_00000000#, + Timer_DMA_COM => 2#00100000_00000000#, + Timer_DMA_Trigger => 2#01000000_00000000#); + -- TODO: consider using a packed array of booleans in the SR representation + -- instead of bit-patterns, thereby obviating this rep clause + + procedure Enable_DMA_Source + (This : in out Timer; + Source : Timer_DMA_Source) + with + Pre => + ((if Basic_Timer (This) then Source = Timer_DMA_Update) and + (if Source in Timer_DMA_COM | Timer_DMA_Trigger + then Advanced_Timer (This))) + or else DMA_Supported (This), + Post => + DMA_Source_Enabled (This, Source); + + procedure Disable_DMA_Source + (This : in out Timer; + Source : Timer_DMA_Source) + with + Pre => + ((if Basic_Timer (This) then Source = Timer_DMA_Update) and + (if Source in Timer_DMA_COM | Timer_DMA_Trigger + then Advanced_Timer (This))) + or else DMA_Supported (This), + Post => + not DMA_Source_Enabled (This, Source); + + function DMA_Source_Enabled + (This : Timer; + Source : Timer_DMA_Source) + return Boolean + with + Pre => + ((if Basic_Timer (This) then Source = Timer_DMA_Update) and + (if Source in Timer_DMA_COM | Timer_DMA_Trigger + then Advanced_Timer (This))) + or else DMA_Supported (This); + + type Timer_DMA_Burst_Length is + (DMA_Burst_Length_1, + DMA_Burst_Length_2, + DMA_Burst_Length_3, + DMA_Burst_Length_4, + DMA_Burst_Length_5, + DMA_Burst_Length_6, + DMA_Burst_Length_7, + DMA_Burst_Length_8, + DMA_Burst_Length_9, + DMA_Burst_Length_10, + DMA_Burst_Length_11, + DMA_Burst_Length_12, + DMA_Burst_Length_13, + DMA_Burst_Length_14, + DMA_Burst_Length_15, + DMA_Burst_Length_16, + DMA_Burst_Length_17, + DMA_Burst_Length_18); + + type Timer_DMA_Base_Address is + (DMA_Base_CR1, + DMA_Base_CR2, + DMA_Base_SMCR, + DMA_Base_DIER, + DMA_Base_SR, + DMA_Base_EGR, + DMA_Base_CCMR1, + DMA_Base_CCMR2, + DMA_Base_CCER, + DMA_Base_CNT, + DMA_Base_PSC, + DMA_Base_ARR, + DMA_Base_RCR, + DMA_Base_CCR1, + DMA_Base_CCR2, + DMA_Base_CCR3, + DMA_Base_CCR4, + DMA_Base_BDTR, + DMA_Base_DCR, + DMA_Base_OR); + + procedure Configure_DMA + (This : in out Timer; + Base_Address : Timer_DMA_Base_Address; + Burst_Length : Timer_DMA_Burst_Length); + + procedure Enable_Capture_Compare_DMA + (This : in out Timer); + + procedure Disable_Capture_Compare_DMA + (This : in out Timer); + + ---------------------------------------------------------------------------- + + -- Output Compare Management ---------------------------------------------- + + ---------------------------------------------------------------------------- + + type Timer_Channel is (Channel_1, Channel_2, Channel_3, Channel_4); + + procedure Enable_Channel + (This : in out Timer; + Channel : Timer_Channel) + with + Pre => not Basic_Timer (This), + Post => Channel_Enabled (This, Channel); + + procedure Disable_Channel + (This : in out Timer; + Channel : Timer_Channel) + with + Pre => not Basic_Timer (This), + Post => not Channel_Enabled (This, Channel); + + function Channel_Enabled + (This : Timer; Channel : Timer_Channel) + return Boolean; + + procedure Enable_Complementary_Channel + (This : in out Timer; + Channel : Timer_Channel) + with + Pre => Complementary_Outputs_Supported (This, Channel), + Post => Complementary_Channel_Enabled (This, Channel); + + procedure Disable_Complementary_Channel + (This : in out Timer; + Channel : Timer_Channel) + with + Pre => Complementary_Outputs_Supported (This, Channel), + Post => not Complementary_Channel_Enabled (This, Channel); + + function Complementary_Channel_Enabled + (This : Timer; Channel : Timer_Channel) + return Boolean + with Pre => Complementary_Outputs_Supported (This, Channel); + + Timer_Channel_Access_Error : exception; + -- Raised when accessing a given channel configuration with the wrong view: + -- as an input when it is set to be an output, and vice versa + + type Timer_Output_Compare_And_PWM_Mode is + (Frozen, + Active, + Inactive, + Toggle, + Force_Inactive, + Force_Active, + PWM1, + PWM2); + -- See RM pg 560 for the effects of these values + + type Timer_Capture_Compare_State is (Disable, Enable); + + type Timer_Output_Compare_Polarity is (High, Low); + + procedure Configure_Channel_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + State : Timer_Capture_Compare_State; + Pulse : UInt32; + Polarity : Timer_Output_Compare_Polarity) + with + Pre => (CC_Channel_Exists (This, Channel) and + Specific_Channel_Output_Supported (This, Channel)) and + (if not Has_32bit_CC_Values (This) then Pulse <= 16#FFFF#), + Post => (if State = Enable + then Channel_Enabled (This, Channel) + else not Channel_Enabled (This, Channel)); + + procedure Set_Compare_Value + (This : in out Timer; + Channel : Timer_Channel; + Word_Value : UInt32) + with + Pre => Has_32bit_CC_Values (This), + Post => Current_Capture_Value (This, Channel) = Word_Value; + + procedure Set_Compare_Value + (This : in out Timer; + Channel : Timer_Channel; + Value : UInt16) + with + Pre => CC_Channel_Exists (This, Channel), + Post => Current_Capture_Value (This, Channel) = Value; + + type Timer_Capture_Compare_Modes is + (Output, Direct_TI, Indirect_TI, TRC); + + function Current_Capture_Compare_Mode + (This : Timer; + Channel : Timer_Channel) + return Timer_Capture_Compare_Modes; + + -- A convenience routine that sets the capture/compare selection to be that + -- of a single channel output and assigns all the controls of that output, + -- as an alternative to calling the individual routines. Does not raise the + -- access error exception because it explicitly sets the mode to Output. + procedure Set_Single_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + OC_Clear_Enabled : Boolean; + Preload_Enabled : Boolean; + Fast_Enabled : Boolean) + with + Pre => CC_Channel_Exists (This, Channel), + Post => Current_Capture_Compare_Mode (This, Channel) = Output; + + procedure Set_Output_Compare_Mode + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode) + with + Pre => (not Basic_Timer (This)) and + (if Current_Capture_Compare_Mode (This, Channel) /= Output + then raise Timer_Channel_Access_Error); + + procedure Set_Output_Preload_Enable + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + with + Pre => CC_Channel_Exists (This, Channel) and + (if Current_Capture_Compare_Mode (This, Channel) /= Output + then raise Timer_Channel_Access_Error); + + procedure Set_Output_Fast_Enable + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + with + Pre => CC_Channel_Exists (This, Channel) and + (if Current_Capture_Compare_Mode (This, Channel) /= Output + then raise Timer_Channel_Access_Error); + + procedure Set_Clear_Control + (This : in out Timer; + Channel : Timer_Channel; + Enabled : Boolean) + with + Pre => CC_Channel_Exists (This, Channel) and + (if Current_Capture_Compare_Mode (This, Channel) /= Output + then raise Timer_Channel_Access_Error); + + procedure Set_Output_Forced_Action + (This : in out Timer; + Channel : Timer_Channel; + Active : Boolean) + with + Pre => CC_Channel_Exists (This, Channel) and + (if Current_Capture_Compare_Mode (This, Channel) /= Output + then raise Timer_Channel_Access_Error); + + procedure Set_Output_Polarity + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Output_Compare_Polarity) + with + Pre => not Basic_Timer (This); + + procedure Set_Output_Complementary_Polarity + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Output_Compare_Polarity) + with + Pre => Advanced_Timer (This); + + -- Indicates whether all outputs are disabled for all channels of the given + -- timer. + function No_Outputs_Enabled (This : Timer) return Boolean; + + ---------------------------------------------------------------------------- + + -- Input Capture Management ----------------------------------------------- + + ---------------------------------------------------------------------------- + + type Timer_Input_Capture_Filter is mod 16; + + type Timer_Input_Capture_Polarity is (Rising, Falling, Both_Edges); + + subtype Timer_Input_Capture_Selection is Timer_Capture_Compare_Modes + range Direct_TI .. TRC; + + type Timer_Input_Capture_Prescaler is + (Div1, -- Capture performed each time an edge is detected on input + Div2, -- Capture performed once every 2 events + Div4, -- Capture performed once every 4 events + Div8); -- Capture performed once every 8 events + + procedure Configure_Channel_Input + (This : in out Timer; + Channel : Timer_Channel; + Polarity : Timer_Input_Capture_Polarity; + Selection : Timer_Input_Capture_Selection; + Prescaler : Timer_Input_Capture_Prescaler; + Filter : Timer_Input_Capture_Filter) + with + Pre => CC_Channel_Exists (This, Channel) and + (if Filter > 7 then Advanced_Timer (This)), + Post => Channel_Enabled (This, Channel) and + Current_Capture_Compare_Mode (This, Channel) = Selection; + + procedure Configure_Channel_Input_PWM + (This : in out Timer; + Channel : Timer_Channel; + Selection : Timer_Input_Capture_Selection; + Polarity : Timer_Input_Capture_Polarity; + Prescaler : Timer_Input_Capture_Prescaler; + Filter : Timer_Input_Capture_Filter) + with + Pre => Has_At_Least_2_CC_Channels (This) and + Channel in Channel_1 | Channel_2, + Post => Channel_Enabled (This, Channel) and + Current_Capture_Compare_Mode (This, Channel) = Selection and + Current_Input_Prescaler (This, Channel) = Prescaler; + + procedure Set_Input_Prescaler + (This : in out Timer; + Channel : Timer_Channel; + Value : Timer_Input_Capture_Prescaler) + with + Pre => not Basic_Timer (This) and + Current_Capture_Compare_Mode (This, Channel) /= Output, + Post => Current_Input_Prescaler (This, Channel) = Value; + + function Current_Input_Prescaler + (This : Timer; + Channel : Timer_Channel) + return Timer_Input_Capture_Prescaler; + + function Current_Capture_Value + (This : Timer; + Channel : Timer_Channel) + return UInt32; + -- Reading the upper reserved area of the CCR register does no harm when + -- the timer does not support 32-bit CC registers so we do not protect + -- this function with a precondition. + + function Current_Capture_Value + (This : Timer; + Channel : Timer_Channel) + return UInt16; + + ---------------------------------------------------------------------------- + + -- Advanced control timers ------------------------------------------------ + + ---------------------------------------------------------------------------- + + procedure Enable_Main_Output (This : in out Timer) + with + Pre => Advanced_Timer (This), + Post => Main_Output_Enabled (This); + + procedure Disable_Main_Output (This : in out Timer) + with + Pre => Advanced_Timer (This), + Post => (if No_Outputs_Enabled (This) then + not Main_Output_Enabled (This)); + + function Main_Output_Enabled (This : Timer) return Boolean; + + procedure Configure + (This : in out Timer; + Prescaler : UInt16; + Period : UInt32; + Clock_Divisor : Timer_Clock_Divisor; + Counter_Mode : Timer_Counter_Alignment_Mode; + Repetitions : UInt8) + with + Pre => Advanced_Timer (This) and + (if Period > UInt32 (UInt16'Last) then Has_32bit_Counter (This)), + Post => Current_Prescaler (This) = Prescaler and + Current_Autoreload (This) = Period; + + procedure Configure_Channel_Output + (This : in out Timer; + Channel : Timer_Channel; + Mode : Timer_Output_Compare_And_PWM_Mode; + State : Timer_Capture_Compare_State; + Pulse : UInt32; + Polarity : Timer_Output_Compare_Polarity; + Idle_State : Timer_Capture_Compare_State; + Complementary_Polarity : Timer_Output_Compare_Polarity; + Complementary_Idle_State : Timer_Capture_Compare_State) + with + Pre => Advanced_Timer (This) and + (if not Has_32bit_CC_Values (This) then Pulse <= 16#FFFF#), + Post => (if State = Enable + then Channel_Enabled (This, Channel) + else not Channel_Enabled (This, Channel)); + + procedure Enable_CC_Preload_Control (This : in out Timer) + with Pre => Advanced_Timer (This); + + procedure Disable_CC_Preload_Control (This : in out Timer) + with Pre => Advanced_Timer (This); + + procedure Select_Commutation (This : in out Timer) + with Pre => Advanced_Timer (This); + + procedure Deselect_Commutation (This : in out Timer) + with Pre => Advanced_Timer (This); + + type Timer_Break_Polarity is (Low, High); + + type Timer_Lock_Level is (Off, Level_1, Level_2, Level_3); + + procedure Configure_BDTR + (This : in out Timer; + Automatic_Output_Enabled : Boolean; + Break_Polarity : Timer_Break_Polarity; + Break_Enabled : Boolean; + Off_State_Selection_Run_Mode : Bit; + Off_State_Selection_Idle_Mode : Bit; + Lock_Configuration : Timer_Lock_Level; + Deadtime_Generator : UInt8) + with Pre => Advanced_Timer (This); + + ---------------------------------------------------------------------------- + + -- Synchronization Management --------------------------------------------- + + ---------------------------------------------------------------------------- + + type Timer_Trigger_Input_Source is + (Internal_Trigger_0, -- ITR0 + Internal_Trigger_1, -- ITR1 + Internal_Trigger_2, -- ITR2 + Internal_Trigger_3, -- ITR3 + TI1_Edge_Detector, -- TI1F_ED + Filtered_Timer_Input_1, -- TI1FP1 + Filtered_Timer_Input_2, -- TI2FP2 + External_Trigger_Input); -- ETRF + + procedure Select_Input_Trigger + (This : in out Timer; + Source : Timer_Trigger_Input_Source) + with Pre => not Basic_Timer (This); + + type Timer_Trigger_Output_Source is + (Reset, + Enable, + Update, + OC1, + OC1Ref, + OC2Ref, + OC3Ref, + OC4Ref); + + procedure Select_Output_Trigger + (This : in out Timer; + Source : Timer_Trigger_Output_Source) + with Pre => Trigger_Output_Selectable (This); -- any of Timer 1 .. 8 + + type Timer_Slave_Mode is + (Disabled, + -- counter counts up/down on TI1 edge + Encoder_Mode_TI1, + -- counter counts up/down on TI2 edge + Encoder_Mode_TI2, + -- counter counts up/down on both TI1 & TI2 edges + Encoder_Mode_TI1_TI2, + Reset, + Gated, + Trigger, + External_1); + + procedure Select_Slave_Mode + (This : in out Timer; + Mode : Timer_Slave_Mode) + with Pre => Slave_Mode_Supported (This); + + procedure Enable_Master_Slave_Mode (This : in out Timer) + with Pre => Slave_Mode_Supported (This); + + procedure Disable_Master_Slave_Mode (This : in out Timer) + with Pre => Slave_Mode_Supported (This); + + type Timer_External_Trigger_Polarity is (Inverted, Noninverted); + + type Timer_External_Trigger_Prescaler is + (Off, + Div2, + Div4, + Div8); + + type Timer_External_Trigger_Filter is mod 16; + + procedure Configure_External_Trigger + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + with Pre => External_Trigger_Supported (This); + + ---------------------------------------------------------------------------- + + -- Clocks Management ------------------------------------------------------ + + ---------------------------------------------------------------------------- + + procedure Select_Internal_Clock + (This : in out Timer) + renames Disable_Master_Slave_Mode; + + subtype Timer_Internal_Trigger_Source is Timer_Trigger_Input_Source + range Internal_Trigger_0 .. Internal_Trigger_3; + + procedure Configure_As_External_Clock + (This : in out Timer; + Source : Timer_Internal_Trigger_Source) + with Pre => Clock_Management_Supported (This); + + subtype Timer_External_Clock_Source is Timer_Trigger_Input_Source + range TI1_Edge_Detector .. Filtered_Timer_Input_2; + + procedure Configure_As_External_Clock + (This : in out Timer; + Source : Timer_External_Clock_Source; + Polarity : Timer_Input_Capture_Polarity; + Filter : Timer_Input_Capture_Filter) + with Pre => not Basic_Timer (This); + + procedure Configure_External_Clock_Mode1 + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + with Pre => External_Trigger_Supported (This); + + procedure Configure_External_Clock_Mode2 + (This : in out Timer; + Polarity : Timer_External_Trigger_Polarity; + Prescaler : Timer_External_Trigger_Prescaler; + Filter : Timer_External_Trigger_Filter) + with Pre => External_Trigger_Supported (This); + + ---------------------------------------------------------------------------- + + -- Misc functions --------------------------------------------------------- + + ---------------------------------------------------------------------------- + + subtype Timer_Encoder_Mode is + Timer_Slave_Mode range Encoder_Mode_TI1 .. Encoder_Mode_TI1_TI2; + + procedure Configure_Encoder_Interface + (This : in out Timer; + Mode : Timer_Encoder_Mode; + IC1_Polarity : Timer_Input_Capture_Polarity; + IC2_Polarity : Timer_Input_Capture_Polarity) + with Pre => Has_At_Least_2_CC_Channels (This); + + procedure Enable_Hall_Sensor + (This : in out Timer) + with Pre => Hall_Sensor_Supported (This); + + procedure Disable_Hall_Sensor + (This : in out Timer) + with Pre => Hall_Sensor_Supported (This); + + type Timer_2_Remapping_Options is -- see RM pg 632 + (TIM2_TIM8_TRGO, + TIM2_ETH_PTP, + TIM2_USBFS_SOF, + TIM2_USBHS_SOF); + + procedure Configure_Timer_2_Remapping + (This : in out Timer; + Option : Timer_2_Remapping_Options) + with Pre => This'Address = STM32_SVD.TIM2_Base; + + type Timer_5_Remapping_Options is -- see RM pg 633 + (TIM5_GPIO, + TIM5_LSI, + TIM5_LSE, + TIM5_RTC); + + procedure Configure_Timer_5_Remapping + (This : in out Timer; + Option : Timer_5_Remapping_Options) + with Pre => This'Address = STM32_SVD.TIM5_Base; + + type Timer_11_Remapping_Options is + (TIM11_GPIO, + TIM11_HSE); + + for Timer_11_Remapping_Options use -- per RM page 676 + (TIM11_GPIO => 0, + TIM11_HSE => 2); + + procedure Configure_Timer_11_Remapping + (This : in out Timer; + Option : Timer_11_Remapping_Options) + with Pre => This'Address = STM32_SVD.TIM11_Base; + + ---------------------------------------------------------------------------- + + -- Classifier functions --------------------------------------------------- + + ---------------------------------------------------------------------------- + + function Basic_Timer (This : Timer) return Boolean; + + -- Timers 1 and 8 + function Advanced_Timer (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 2 and 5 + function Has_32bit_Counter (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM2_Base or + -- The RM register map for timers 2 through 5, pg 634, indicates that + -- only timer 2 and timer 5 actually have the upper half of the counter + -- available, and that the others must keep it reserved. This would + -- appear to contradict the text in the introduction to those timers, + -- but section 18.2 indicates the restriction explicitly. + This'Address = STM32_SVD.TIM5_Base); + + -- Timers 2 and 5 + function Has_32bit_CC_Values (This : Timer) return Boolean + renames Has_32bit_Counter; + + -- Timers 1 .. 8 + function Trigger_Output_Selectable (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 1 .. 5, 8, 9, 12 + function Has_At_Least_2_CC_Channels (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base or + This'Address = STM32_SVD.TIM9_Base); + + -- Timers 1 .. 5, 8 + function Hall_Sensor_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 1 .. 5, 8, 9, 12 + function Clock_Management_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base or + This'Address = STM32_SVD.TIM9_Base); + + -- Timers 1 .. 5, 8 + function Has_At_Least_3_CC_Channels (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 1 .. 5, 8 + function Has_At_Least_4_CC_Channels (This : Timer) return Boolean + renames Has_At_Least_3_CC_Channels; + + -- Not all timers have four channels available for capture/compare + function CC_Channel_Exists (This : Timer; + Channel : Timer_Channel) + return Boolean + is + ((if Channel = Channel_1 then not Basic_Timer (This)) or + (if Channel = Channel_2 then Has_At_Least_2_CC_Channels (This)) or + (if Channel = Channel_3 then Has_At_Least_3_CC_Channels (This)) or + (if Channel = Channel_4 then Has_At_Least_4_CC_Channels (This))); + + -- Timers 1 .. 5, 8 + function Input_XOR_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 1 .. 8 + function DMA_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 1 .. 5, 8, 9, 12 + function Slave_Mode_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base or + This'Address = STM32_SVD.TIM9_Base); + + -- Timers 1 .. 5, 8 + function External_Trigger_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base); + + -- Timers 2, 5, 11 + function Remapping_Capability_Supported (This : Timer) return Boolean is + (This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM11_Base); + + -- Not all timers support output on all channels + function Specific_Channel_Output_Supported + (This : Timer; Channel : Timer_Channel) + return Boolean + is + (This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM2_Base or + This'Address = STM32_SVD.TIM3_Base or + This'Address = STM32_SVD.TIM4_Base or + This'Address = STM32_SVD.TIM5_Base or + This'Address = STM32_SVD.TIM8_Base + -- all the above can be with any of the four channels + or + (This'Address = STM32_SVD.TIM9_Base and + Channel in Channel_1 | Channel_2) + or + (This'Address = STM32_SVD.TIM10_Base and + Channel = Channel_1) + or + (This'Address = STM32_SVD.TIM11_Base and + Channel = Channel_1)); + + -- Timers 1 and 8, channels 1 .. 3 + function Complementary_Outputs_Supported + (This : Timer; Channel : Timer_Channel) + return Boolean + is + ((This'Address = STM32_SVD.TIM1_Base or + This'Address = STM32_SVD.TIM8_Base) and + Channel in Channel_1 | Channel_2 | Channel_3); + +private + + type TIMx_CR1 is record + Reserved : UInt6; + Clock_Division : Timer_Clock_Divisor; + ARPE : Boolean; -- Auto-reload preload enable + Mode_And_Dir : Timer_Counter_Alignment_Mode; + One_Pulse_Mode : Timer_One_Pulse_Mode; + Update_Request_Source : Boolean; + Update_Disable : Boolean; + Timer_Enabled : Boolean; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_CR1 use record + Reserved at 0 range 10 .. 15; + Clock_Division at 0 range 8 .. 9; + ARPE at 0 range 7 .. 7; + Mode_And_Dir at 0 range 4 .. 6; + One_Pulse_Mode at 0 range 3 .. 3; + Update_Request_Source at 0 range 2 .. 2; + Update_Disable at 0 range 1 .. 1; + Timer_Enabled at 0 range 0 .. 0; + end record; + + ------------------------ representation for CR2 -------------------------- + + type TIMx_CR2 is record + Reserved0 : UInt16; + Reserved1 : Bit; + Channel_4_Output_Idle_State : Timer_Capture_Compare_State; + Channel_3_Complementary_Output_Idle_State : Timer_Capture_Compare_State; + Channel_3_Output_Idle_State : Timer_Capture_Compare_State; + Channel_2_Complementary_Output_Idle_State : Timer_Capture_Compare_State; + Channel_2_Output_Idle_State : Timer_Capture_Compare_State; + Channel_1_Complementary_Output_Idle_State : Timer_Capture_Compare_State; + Channel_1_Output_Idle_State : Timer_Capture_Compare_State; + TI1_Selection : Boolean; + Master_Mode_Selection : Timer_Trigger_Output_Source; + Capture_Compare_DMA_Selection : Boolean; + Capture_Compare_Control_Update_Selection : Boolean; + Reserved2 : Bit; + Capture_Compare_Preloaded_Control : Boolean; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_CR2 use record + Reserved0 at 0 range 16 .. 31; + Reserved1 at 0 range 15 .. 15; + Channel_4_Output_Idle_State at 0 range 14 .. 14; + Channel_3_Complementary_Output_Idle_State at 0 range 13 .. 13; + Channel_3_Output_Idle_State at 0 range 12 .. 12; + Channel_2_Complementary_Output_Idle_State at 0 range 11 .. 11; + Channel_2_Output_Idle_State at 0 range 10 .. 10; + Channel_1_Complementary_Output_Idle_State at 0 range 9 .. 9; + Channel_1_Output_Idle_State at 0 range 8 .. 8; + TI1_Selection at 0 range 7 .. 7; + Master_Mode_Selection at 0 range 4 .. 6; + Capture_Compare_DMA_Selection at 0 range 3 .. 3; + Capture_Compare_Control_Update_Selection at 0 range 2 .. 2; + Reserved2 at 0 range 1 .. 1; + Capture_Compare_Preloaded_Control at 0 range 0 .. 0; + end record; + + ------------ representation for slave mode control register -------------- + + type TIMx_SMCR is record + Reserved0 : UInt16; + External_Trigger_Polarity : Timer_External_Trigger_Polarity; + External_Clock_Enable : Boolean; + External_Trigger_Prescaler : Timer_External_Trigger_Prescaler; + External_Trigger_Filter : Timer_External_Trigger_Filter; + Master_Slave_Mode : Boolean; + Trigger_Selection : Timer_Trigger_Input_Source; + Reserved1 : Bit; + Slave_Mode_Selection : Timer_Slave_Mode; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_SMCR use record + Reserved0 at 0 range 16 .. 31; + External_Trigger_Polarity at 0 range 15 .. 15; + External_Clock_Enable at 0 range 14 .. 14; + External_Trigger_Prescaler at 0 range 12 .. 13; + External_Trigger_Filter at 0 range 8 .. 11; + Master_Slave_Mode at 0 range 7 .. 7; + Trigger_Selection at 0 range 4 .. 6; + Reserved1 at 0 range 3 .. 3; + Slave_Mode_Selection at 0 range 0 .. 2; + end record; + + ------------ representation for CCMR1 and CCMR2 -------------------------- + + -- Per the ST Reference Manual, there are two words (registers) + -- allocated within a timer to describe the capture-compare input/output + -- configurations for the four channels. These are CCMR1 and CCMR2. Both + -- currently only use the lower half of the word, with the upper half + -- reserved. + + -- Each description is either that of a single input or a single output + -- for the given channel. Both kinds of description require eight + -- bits, therefore there are two channel descriptions in each word. + + -- Although both the input and output descriptions are the same size in + -- terms of bits (six bits each), they do not have the same logical fields. + -- We use two distinct types to represent individual input and output + -- descriptions. + + type Channel_Output_Descriptor is record + OCxFast_Enable : Boolean; + OCxPreload_Enable : Boolean; + OCxMode : Timer_Output_Compare_And_PWM_Mode; + OCxClear_Enable : Boolean; + end record with Size => 6; + + for Channel_Output_Descriptor use record + OCxFast_Enable at 0 range 0 .. 0; + OCxPreload_Enable at 0 range 1 .. 1; + OCxMode at 0 range 2 .. 4; + OCxClear_Enable at 0 range 5 .. 5; + end record; + + type Channel_Input_Descriptor is record + ICxFilter : Timer_Input_Capture_Filter; + ICxPrescaler : Timer_Input_Capture_Prescaler; + end record with Size => 6; + + for Channel_Input_Descriptor use record + ICxFilter at 0 range 2 .. 5; + ICxPrescaler at 0 range 0 .. 1; + end record; + + -- So any given eight-bit description uses six bits for the specific fields + -- describing the input or output configuration. The other two bits are + -- taken by a field selecting the kind of description, i.e., either an + -- input or an output description. In the RM register definitions this + -- is "CCxS" (where 'x' is a place-holder for a channel number). Although + -- there is one kind of output, there are in fact three kinds of inputs. + + -- Thus any given channel description is an eight-bit quantity that + -- both indicates the kind and contains another set of dependent fields + -- representing that kind. The dependent fields are logically mutually + -- exclusive, i.e., if the CCxS selection field indicates an input then + -- the output fields are not present, and vice versa. This logical layout + -- is naturally represented in Ada as a discriminated type, where the + -- discriminant is the CCxS "Selection" indicator. + + -- Note that the discriminant default value "Output" matches the default + -- value of the hardware register bits when the device is powered up. + -- Therefore we don't strictly speaking need pragma Import on the + -- declarations of Timer objects, but it won't hurt. + + type IO_Descriptor (CCxSelection : Timer_Capture_Compare_Modes := Output) is + record + case CCxSelection is + when Direct_TI .. TRC => + Capture : Channel_Input_Descriptor; + when Output => + Compare : Channel_Output_Descriptor; + end case; + end record with Size => 8; + + -- Per the RM, the input fields and the output fields are in the same + -- locations in memory, that is, they overlay, coming after the common + -- CCxS field. + + for IO_Descriptor use record + CCxSelection at 0 range 0 .. 1; + Capture at 0 range 2 .. 7; + Compare at 0 range 2 .. 7; + end record; + + -- Thus we have a means of describing any single channel's configuration + -- as either an input or an output. But how to get to them? As mentioned + -- above, there are four channels so there are four I/O descriptions, + -- spread across the two words of CCMR1 and CCMR2 in the timer + -- representation. Specifically, the descriptions for channels 1 and 2 are + -- in CCMR1, and the descriptions for channels 3 and 4 are in CCMR2. Rather + -- than determine which register to use by having a dedicated routine + -- for each channel, we use an array of descriptions allocated across the + -- memory for the two registers and compute the description to use within + -- the array for that channel. + -- + -- The remaining difficulty is the reserved upper halves of each of the + -- two registers in memory. We cannot simply allocate four components in + -- our array because we must skip the reserved areas, but we don't have + -- non-contiguous arrays in Ada (nor should we). As a result we must + -- either declare two arrays, each with two descriptions, thus requiring + -- additional types to specify the reserved areas, or we declare one + -- array of eight descriptions and only access the four "real" ones. If we + -- take the latter approach the other four descriptions would occupy the + -- reserved areas and would never be accessed. As long as the reserved + -- areas remain at their reset values (all zeroes) all should be well... + -- except that we also have the requirement to access the memory for the + -- two registers as either half-words or words, so any simplicity gained + -- from declaring an array larger than required would be lost when + -- processing it. Hence the following takes the first approach, not + -- mapping anything to the reserved upper halves of the two words. + + subtype Lower_Half_Index is Integer range 1 .. 2; + + type TIMx_CCMRx_Lower_Half is + array (Lower_Half_Index) of IO_Descriptor + with Volatile_Components, Component_Size => 8, Size => 16; + + type TIMx_CCMRx is record + Descriptors : TIMx_CCMRx_Lower_Half; + Reserved : UInt16; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_CCMRx use record + Descriptors at 0 range 0 .. 15; + Reserved at 0 range 16 .. 31; + end record; + + -- Then we can define the array of this final record type TIMx_CCMRx, + -- taking the space of the two CCMR1 and CCMR2 register words in memory. + + subtype CCMRx_Index is Integer range 1 .. 2; + + type TIMx_CCMR_Pair is array (CCMRx_Index) of TIMx_CCMRx + with Component_Size => 32, Size => 64; + + -- Is this better than using bit masks? There's certainly a good bit more + -- required for the declarations of the data structure! But the access code + -- is pretty small and we would argue that the compile-time checking, and + -- the readability, imply greater robustness and maintainability. (That + -- said, the existing C libraries are very stable and mature.) This part + -- of the hardware is definitely complicated in itself, and overlaying the + -- input and output descriptions in memory didn't help. Performance should + -- be reasonable, although not as good as bit-masking would be. Nowadays + -- that's not necessarily where the money is, so we go with this approach + -- for now... + + procedure Write_Channel_Input_Description + (This : in out Timer; + Channel : Timer_Channel; + Kind : Timer_Input_Capture_Selection; + Description : Channel_Input_Descriptor) + with Pre => not Channel_Enabled (This, Channel); + + ------------ representation for the CCER --------------------------------- + + -- The CCER register is composed of a logical grouping of four sets of + -- bits, one per channel. The type Single_CCE describe these four bits. + -- Channels 1 through 3 have all four bits, but channel 4 does not have + -- the complementary state and polarity bits. We pretend that it does for + -- the type declaration and then treat it accordingly in the accessing + -- subprograms. + + type Single_CCE is record + CCxE : Timer_Capture_Compare_State; + CCxP : Bit; + CCxNE : Timer_Capture_Compare_State; + CCxNP : Bit; + end record with Size => 4; + + for Single_CCE use record + CCxE at 0 range 0 .. 0; + CCxP at 0 range 1 .. 1; + CCxNE at 0 range 2 .. 2; + CCxNP at 0 range 3 .. 3; + end record; + + type TIMx_CCER is array (Timer_Channel) of Single_CCE + with Volatile_Full_Access, Component_Size => 4, Size => 16; + + -------- representation for CCR1 through CCR4 ---------------------------- + + -- Instead of declaring four individual record components, one per channel, + -- each one a word in size, we just declare an array component representing + -- all four values, indexed by the channel. Timers 2 and 5 actually use all + -- 32 bits of each, the other timers only use the lower half. + + type Capture_Compare_Registers is array (Timer_Channel) of UInt32 + with Volatile_Components, Component_Size => 32, Size => 128; + + ---------- representation for the Break and Dead Time Register - ---------- + + type TIMx_BDTR is record + Reserved : UInt16; + Main_Output_Enabled : Boolean; + Automatic_Output_Enabled : Boolean; + Break_Polarity : Timer_Break_Polarity; + Break_Enable : Boolean; + Off_State_Selection_Run_Mode : Bit; + Off_State_Selection_Idle_Mode : Bit; + Lock : Timer_Lock_Level; + Deadtime_Generator : UInt8; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_BDTR use record + Reserved at 0 range 16 .. 31; + Main_Output_Enabled at 0 range 15 .. 15; + Automatic_Output_Enabled at 0 range 14 .. 14; + Break_Polarity at 0 range 13 .. 13; + Break_Enable at 0 range 12 .. 12; + Off_State_Selection_Run_Mode at 0 range 11 .. 11; + Off_State_Selection_Idle_Mode at 0 range 10 .. 10; + Lock at 0 range 8 .. 9; + Deadtime_Generator at 0 range 0 .. 7; + end record; + + ----------- representation for the DMA Control Register type ------------- + + type TIMx_DCR is record + Reserved0 : UInt16; + Reserved1 : UInt3; + Burst_Length : Timer_DMA_Burst_Length; + Reserved2 : UInt3; + Base_Address : Timer_DMA_Base_Address; + end record with Volatile_Full_Access, Size => 32; + + for TIMx_DCR use record + Reserved0 at 0 range 16 .. 31; + Reserved1 at 0 range 13 .. 15; + Burst_Length at 0 range 8 .. 12; + Reserved2 at 0 range 5 .. 7; + Base_Address at 0 range 0 .. 4; + end record; + + ------- representation for Timer 2, 5, and 11 remapping options ---------- + + type TIMx_OR is record + Reserved0 : UInt16; + Reserved1 : UInt4; + ITR1_RMP : Timer_2_Remapping_Options; + Reserved2 : UInt2; + TI4_RMP : Timer_5_Remapping_Options; -- timer 5, pg 633 + Reserved3 : UInt4; + TI1_RMP : Timer_11_Remapping_Options; -- timer 11, pg 676 + end record with Volatile_Full_Access, Size => 32; + + -- TODO: ensure the gaps are kept at reserved value in the routines' + -- generated code + + for TIMx_OR use record + Reserved0 at 0 range 16 .. 31; + Reserved1 at 0 range 12 .. 15; + ITR1_RMP at 0 range 10 .. 11; + Reserved2 at 0 range 8 .. 9; + TI4_RMP at 0 range 6 .. 7; + Reserved3 at 0 range 2 .. 5; + TI1_RMP at 0 range 0 .. 1; + end record; + + ---------------- representation for the whole Timer type ----------------- + + type Timer is limited record + CR1 : TIMx_CR1; + CR2 : TIMx_CR2; + SMCR : TIMx_SMCR; + DIER : UInt32; + SR : UInt32; + EGR : UInt32; + CCMR1_2 : TIMx_CCMR_Pair; + CCER : TIMx_CCER; + Reserved_CCER : UInt16; + Counter : UInt32 with Atomic; + -- a full word for timers 2 and 5 only + Prescaler : UInt16; + Reserved_Prescaler : UInt16; + ARR : UInt32; + RCR : UInt32; + CCR1_4 : Capture_Compare_Registers; + BDTR : TIMx_BDTR; + DCR : TIMx_DCR; + DMAR : UInt32; + Options : TIMx_OR; + end record with Volatile, Size => 21 * 32; + + for Timer use record + CR1 at 16#00# range 0 .. 31; + CR2 at 16#04# range 0 .. 31; + SMCR at 16#08# range 0 .. 31; + DIER at 16#0C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCMR1_2 at 16#18# range 0 .. 63; + CCER at 16#20# range 0 .. 15; + Reserved_CCER at 16#20# range 16 .. 31; + Counter at 16#24# range 0 .. 31; + Prescaler at 16#28# range 0 .. 15; + Reserved_Prescaler at 16#28# range 16 .. 31; + ARR at 16#2C# range 0 .. 31; + RCR at 16#30# range 0 .. 31; + CCR1_4 at 16#34# range 0 .. 127; -- ie, 4 words + BDTR at 16#44# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + Options at 16#50# range 0 .. 31; + end record; + +end STM32.Timers; diff --git a/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.adb b/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.adb new file mode 100644 index 000000000..66273b743 --- /dev/null +++ b/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.adb @@ -0,0 +1,579 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2017, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_usart.c -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief USARTS HAL module driver. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +with System; use System; +with STM32_SVD.USART; use STM32_SVD, STM32_SVD.USART; + +with STM32.Device; use STM32.Device; + +package body STM32.USARTs is + + --------------- + -- APB_Clock -- + --------------- + + function APB_Clock (This : USART) return UInt32 is + Clocks : constant RCC_System_Clocks := System_Clock_Frequencies; + begin + if This.Periph.all'Address = USART1_Base + or + This.Periph.all'Address = USART6_Base + then + return Clocks.PCLK2; + else + return Clocks.PCLK1; + end if; + end APB_Clock; + + ------------ + -- Enable -- + ------------ + + procedure Enable (This : in out USART) is + begin + This.Periph.CR1.UE := True; + end Enable; + + ------------- + -- Disable -- + ------------- + + procedure Disable (This : in out USART) is + begin + This.Periph.CR1.UE := False; + end Disable; + + ------------- + -- Enabled -- + ------------- + + function Enabled (This : USART) return Boolean is + (This.Periph.CR1.UE); + + ------------------- + -- Set_Stop_Bits -- + ------------------- + + procedure Set_Stop_Bits (This : in out USART; To : Stop_Bits) + is + begin + This.Periph.CR2.STOP := Stop_Bits'Enum_Rep (To); + end Set_Stop_Bits; + + --------------------- + -- Set_Word_Length -- + --------------------- + + procedure Set_Word_Length + (This : in out USART; + To : Word_Lengths) + is + begin + This.Periph.CR1.M := To = Word_Length_9; + end Set_Word_Length; + + ---------------- + -- Set_Parity -- + ---------------- + + procedure Set_Parity (This : in out USART; To : Parities) is + begin + case To is + when No_Parity => + This.Periph.CR1.PCE := False; + This.Periph.CR1.PS := False; + when Even_Parity => + This.Periph.CR1.PCE := True; + This.Periph.CR1.PS := False; + when Odd_Parity => + This.Periph.CR1.PCE := True; + This.Periph.CR1.PS := True; + end case; + end Set_Parity; + + ------------------- + -- Set_Baud_Rate -- + ------------------- + + procedure Set_Baud_Rate (This : in out USART; To : Baud_Rates) + is + Clock : constant UInt32 := APB_Clock (This); + Over_By_8 : constant Boolean := This.Periph.CR1.OVER8; + Int_Scale : constant UInt32 := (if Over_By_8 then 2 else 4); + Int_Divider : constant UInt32 := (25 * Clock) / (Int_Scale * To); + Frac_Divider : constant UInt32 := Int_Divider rem 100; + begin + -- the integer part of the divi + if Over_By_8 then + This.Periph.BRR.DIV_Fraction := + BRR_DIV_Fraction_Field (((Frac_Divider * 8) + 50) / 100 mod 8); + else + This.Periph.BRR.DIV_Fraction := + BRR_DIV_Fraction_Field (((Frac_Divider * 16) + 50) / 100 mod 16); + end if; + + This.Periph.BRR.DIV_Mantissa := + BRR_DIV_Mantissa_Field (Int_Divider / 100); + end Set_Baud_Rate; + + --------------------------- + -- Set_Oversampling_Mode -- + --------------------------- + + procedure Set_Oversampling_Mode + (This : in out USART; + To : Oversampling_Modes) + is + begin + This.Periph.CR1.OVER8 := To = Oversampling_By_8; + end Set_Oversampling_Mode; + + -------------- + -- Set_Mode -- + -------------- + + procedure Set_Mode (This : in out USART; To : UART_Modes) is + begin + This.Periph.CR1.RE := To /= Tx_Mode; + This.Periph.CR1.TE := To /= Rx_Mode; + end Set_Mode; + + ---------------------- + -- Set_Flow_Control -- + ---------------------- + + procedure Set_Flow_Control (This : in out USART; To : Flow_Control) is + begin + case To is + when No_Flow_Control => + This.Periph.CR3.RTSE := False; + This.Periph.CR3.CTSE := False; + when RTS_Flow_Control => + This.Periph.CR3.RTSE := True; + This.Periph.CR3.CTSE := False; + when CTS_Flow_Control => + This.Periph.CR3.RTSE := False; + This.Periph.CR3.CTSE := True; + when RTS_CTS_Flow_Control => + This.Periph.CR3.RTSE := True; + This.Periph.CR3.CTSE := True; + end case; + end Set_Flow_Control; + + --------- + -- Put -- + --------- + + procedure Transmit (This : in out USART; Data : UInt9) is + begin + This.Periph.DR.DR := Data; + end Transmit; + + --------- + -- Get -- + --------- + + procedure Receive (This : USART; Data : out UInt9) is + begin + Data := Current_Input (This); + end Receive; + + ------------------- + -- Current_Input -- + ------------------- + + function Current_Input (This : USART) return UInt9 is (This.Periph.DR.DR); + + -------------- + -- Tx_Ready -- + -------------- + + function Tx_Ready (This : USART) return Boolean is + begin + return This.Periph.SR.TXE; + end Tx_Ready; + + -------------- + -- Rx_Ready -- + -------------- + + function Rx_Ready (This : USART) return Boolean is + begin + return This.Periph.SR.RXNE; + end Rx_Ready; + + ------------ + -- Status -- + ------------ + + function Status (This : USART; Flag : USART_Status_Flag) return Boolean is + begin + case Flag is + when Parity_Error_Indicated => + return This.Periph.SR.PE; + when Framing_Error_Indicated => + return This.Periph.SR.FE; + when USART_Noise_Error_Indicated => + return This.Periph.SR.NF; + when Overrun_Error_Indicated => + return This.Periph.SR.ORE; + when Idle_Line_Detection_Indicated => + return This.Periph.SR.IDLE; + when Read_Data_Register_Not_Empty => + return This.Periph.SR.RXNE; + when Transmission_Complete_Indicated => + return This.Periph.SR.TC; + when Transmit_Data_Register_Empty => + return This.Periph.SR.TXE; + when Line_Break_Detection_Indicated => + return This.Periph.SR.LBD; + when Clear_To_Send_Indicated => + return This.Periph.SR.CTS; + end case; + end Status; + + ------------------ + -- Clear_Status -- + ------------------ + + procedure Clear_Status (This : in out USART; Flag : USART_Status_Flag) is + begin + case Flag is + when Parity_Error_Indicated => + This.Periph.SR.PE := False; + when Framing_Error_Indicated => + This.Periph.SR.FE := False; + when USART_Noise_Error_Indicated => + This.Periph.SR.NF := False; + when Overrun_Error_Indicated => + This.Periph.SR.ORE := False; + when Idle_Line_Detection_Indicated => + This.Periph.SR.IDLE := False; + when Read_Data_Register_Not_Empty => + This.Periph.SR.RXNE := False; + when Transmission_Complete_Indicated => + This.Periph.SR.TC := False; + when Transmit_Data_Register_Empty => + This.Periph.SR.TXE := False; + when Line_Break_Detection_Indicated => + This.Periph.SR.LBD := False; + when Clear_To_Send_Indicated => + This.Periph.SR.CTS := False; + end case; + end Clear_Status; + + ----------------------- + -- Enable_Interrupts -- + ----------------------- + + procedure Enable_Interrupts + (This : in out USART; + Source : USART_Interrupt) + is + begin + case Source is + when Parity_Error => + This.Periph.CR1.PEIE := True; + when Transmit_Data_Register_Empty => + This.Periph.CR1.TXEIE := True; + when Transmission_Complete => + This.Periph.CR1.TCIE := True; + when Received_Data_Not_Empty => + This.Periph.CR1.RXNEIE := True; + when Idle_Line_Detection => + This.Periph.CR1.IDLEIE := True; + when Line_Break_Detection => + This.Periph.CR2.LBDIE := True; + when Clear_To_Send => + This.Periph.CR3.CTSIE := True; + when Error => + This.Periph.CR3.EIE := True; + end case; + end Enable_Interrupts; + + ------------------------ + -- Disable_Interrupts -- + ------------------------ + + procedure Disable_Interrupts + (This : in out USART; + Source : USART_Interrupt) + is + begin + case Source is + when Parity_Error => + This.Periph.CR1.PEIE := False; + when Transmit_Data_Register_Empty => + This.Periph.CR1.TXEIE := False; + when Transmission_Complete => + This.Periph.CR1.TCIE := False; + when Received_Data_Not_Empty => + This.Periph.CR1.RXNEIE := False; + when Idle_Line_Detection => + This.Periph.CR1.IDLEIE := False; + when Line_Break_Detection => + This.Periph.CR2.LBDIE := False; + when Clear_To_Send => + This.Periph.CR3.CTSIE := False; + when Error => + This.Periph.CR3.EIE := False; + end case; + end Disable_Interrupts; + + ----------------------- + -- Interrupt_Enabled -- + ----------------------- + + function Interrupt_Enabled + (This : USART; + Source : USART_Interrupt) + return Boolean + is + begin + case Source is + when Parity_Error => + return This.Periph.CR1.PEIE; + when Transmit_Data_Register_Empty => + return This.Periph.CR1.TXEIE; + when Transmission_Complete => + return This.Periph.CR1.TCIE; + when Received_Data_Not_Empty => + return This.Periph.CR1.RXNEIE; + when Idle_Line_Detection => + return This.Periph.CR1.IDLEIE; + when Line_Break_Detection => + return This.Periph.CR2.LBDIE; + when Clear_To_Send => + return This.Periph.CR3.CTSIE; + when Error => + return This.Periph.CR3.EIE; + end case; + end Interrupt_Enabled; + + ---------------------------------- + -- Enable_DMA_Transmit_Requests -- + ---------------------------------- + + procedure Enable_DMA_Transmit_Requests (This : in out USART) is + begin + This.Periph.CR3.DMAT := True; + end Enable_DMA_Transmit_Requests; + + --------------------------------- + -- Enable_DMA_Receive_Requests -- + --------------------------------- + + procedure Enable_DMA_Receive_Requests (This : in out USART) is + begin + This.Periph.CR3.DMAR := True; + end Enable_DMA_Receive_Requests; + + ----------------------------------- + -- Disable_DMA_Transmit_Requests -- + ----------------------------------- + + procedure Disable_DMA_Transmit_Requests (This : in out USART) is + begin + This.Periph.CR3.DMAT := False; + end Disable_DMA_Transmit_Requests; + + ---------------------------------- + -- Disable_DMA_Receive_Requests -- + ---------------------------------- + + procedure Disable_DMA_Receive_Requests (This : in out USART) is + begin + This.Periph.CR3.DMAR := False; + end Disable_DMA_Receive_Requests; + + ----------------------------------- + -- DMA_Transmit_Requests_Enabled -- + ----------------------------------- + + function DMA_Transmit_Requests_Enabled (This : USART) return Boolean is + (This.Periph.CR3.DMAT); + + ---------------------------------- + -- DMA_Receive_Requests_Enabled -- + ---------------------------------- + + function DMA_Receive_Requests_Enabled (This : USART) return Boolean is + (This.Periph.CR3.DMAR); + + ----------------------------- + -- Resume_DMA_Transmission -- + ----------------------------- + + procedure Resume_DMA_Transmission (This : in out USART) is + begin + Enable_DMA_Transmit_Requests (This); + if not Enabled (This) then + Enable (This); + end if; + end Resume_DMA_Transmission; + + -------------------------- + -- Resume_DMA_Reception -- + -------------------------- + + procedure Resume_DMA_Reception (This : in out USART) is + begin + Enable_DMA_Receive_Requests (This); + if not Enabled (This) then + Enable (This); + end if; + end Resume_DMA_Reception; + + --------------------------- + -- Data_Register_Address -- + --------------------------- + + function Data_Register_Address (This : USART) return System.Address is + (This.Periph.DR'Address); + + --------------- + -- Data_Size -- + --------------- + + overriding + function Data_Size (This : USART) return HAL.UART.UART_Data_Size + is + begin + if This.Periph.CR1.M then + return Data_Size_9b; + else + return Data_Size_8b; + end if; + end Data_Size; + + -------------- + -- Transmit -- + -------------- + + overriding + procedure Transmit + (This : in out USART; + Data : UART_Data_8b; + Status : out UART_Status; + Timeout : Natural := 1000) + is + pragma Unreferenced (Status, Timeout); + begin + for Elt of Data loop + loop + exit when This.Tx_Ready; + end loop; + + This.Transmit (UInt9 (Elt)); + end loop; + Status := Ok; + end Transmit; + + -------------- + -- Transmit -- + -------------- + + overriding + procedure Transmit + (This : in out USART; + Data : UART_Data_9b; + Status : out UART_Status; + Timeout : Natural := 1000) + is + pragma Unreferenced (Status, Timeout); + begin + for Elt of Data loop + loop + exit when This.Tx_Ready; + end loop; + + This.Transmit (Elt); + end loop; + Status := Ok; + end Transmit; + + ------------- + -- Receive -- + ------------- + + overriding + procedure Receive + (This : in out USART; + Data : out UART_Data_8b; + Status : out UART_Status; + Timeout : Natural := 1000) + is + pragma Unreferenced (Status, Timeout); + begin + for Elt of Data loop + loop + exit when This.Rx_Ready; + end loop; + + This.Receive (UInt9 (Elt)); + end loop; + Status := Ok; + end Receive; + + ------------- + -- Receive -- + ------------- + + overriding + procedure Receive + (This : in out USART; + Data : out UART_Data_9b; + Status : out UART_Status; + Timeout : Natural := 1000) + is + pragma Unreferenced (Status, Timeout); + begin + for Elt of Data loop + loop + exit when This.Rx_Ready; + end loop; + + This.Receive (Elt); + end loop; + Status := Ok; + end Receive; + +end STM32.USARTs; diff --git a/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.ads b/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.ads new file mode 100644 index 000000000..cb0ab7490 --- /dev/null +++ b/arch/ARM/STM32/drivers/uart_stm32f401/stm32-usarts.ads @@ -0,0 +1,271 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2016, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4xx_hal_usart.h -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief Header file of USARTS HAL module. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides register definitions for the STM32F4 (ARM Cortex M4F) +-- USART from ST Microelectronics. + +-- Note that there are board implementation assumptions represented by the +-- private function APB_Clock. + +with System; +with HAL.UART; use HAL.UART; +private with STM32_SVD.USART; + +package STM32.USARTs is + + type Internal_USART is limited private; + + type USART (Periph : not null access Internal_USART) is + limited new HAL.UART.UART_Port with private; + + procedure Enable (This : in out USART) with + Post => Enabled (This), + Inline; + + procedure Disable (This : in out USART) with + Post => not Enabled (This), + Inline; + + function Enabled (This : USART) return Boolean with Inline; + + procedure Receive (This : USART; Data : out UInt9) with Inline; + -- reads Device.DR into Data + + function Current_Input (This : USART) return UInt9 with Inline; + -- returns Device.DR + + procedure Transmit (This : in out USART; Data : UInt9) with Inline; + + function Tx_Ready (This : USART) return Boolean with Inline; + + function Rx_Ready (This : USART) return Boolean with Inline; + + type Stop_Bits is (Stopbits_1, Stopbits_2) with Size => 2; + + for Stop_Bits use (Stopbits_1 => 0, Stopbits_2 => 2#10#); + + procedure Set_Stop_Bits (This : in out USART; To : Stop_Bits); + + type Word_Lengths is (Word_Length_8, Word_Length_9); + + procedure Set_Word_Length (This : in out USART; To : Word_Lengths); + + type Parities is (No_Parity, Even_Parity, Odd_Parity); + + procedure Set_Parity (This : in out USART; To : Parities); + + subtype Baud_Rates is UInt32; + + procedure Set_Baud_Rate (This : in out USART; To : Baud_Rates); + + type Oversampling_Modes is (Oversampling_By_8, Oversampling_By_16); + -- oversampling by 16 is the default + + procedure Set_Oversampling_Mode + (This : in out USART; + To : Oversampling_Modes); + + type UART_Modes is (Rx_Mode, Tx_Mode, Tx_Rx_Mode); + + procedure Set_Mode (This : in out USART; To : UART_Modes); + + type Flow_Control is + (No_Flow_Control, + RTS_Flow_Control, + CTS_Flow_Control, + RTS_CTS_Flow_Control); + + procedure Set_Flow_Control (This : in out USART; To : Flow_Control); + + type USART_Interrupt is + (Parity_Error, + Transmit_Data_Register_Empty, + Transmission_Complete, + Received_Data_Not_Empty, + Idle_Line_Detection, + Line_Break_Detection, + Clear_To_Send, + Error); + + procedure Enable_Interrupts + (This : in out USART; + Source : USART_Interrupt) + with + Post => Interrupt_Enabled (This, Source), + Inline; + + procedure Disable_Interrupts + (This : in out USART; + Source : USART_Interrupt) + with + Post => not Interrupt_Enabled (This, Source), + Inline; + + function Interrupt_Enabled + (This : USART; + Source : USART_Interrupt) + return Boolean + with Inline; + + type USART_Status_Flag is + (Parity_Error_Indicated, + Framing_Error_Indicated, + USART_Noise_Error_Indicated, + Overrun_Error_Indicated, + Idle_Line_Detection_Indicated, + Read_Data_Register_Not_Empty, + Transmission_Complete_Indicated, + Transmit_Data_Register_Empty, + Line_Break_Detection_Indicated, + Clear_To_Send_Indicated); + + function Status (This : USART; Flag : USART_Status_Flag) return Boolean + with Inline; + + procedure Clear_Status (This : in out USART; Flag : USART_Status_Flag) + with Inline; + + procedure Enable_DMA_Transmit_Requests (This : in out USART) with + Inline, + Post => DMA_Transmit_Requests_Enabled (This); + + procedure Disable_DMA_Transmit_Requests (This : in out USART) with + Inline, + Post => not DMA_Transmit_Requests_Enabled (This); + + function DMA_Transmit_Requests_Enabled (This : USART) return Boolean with + Inline; + + procedure Enable_DMA_Receive_Requests (This : in out USART) with + Inline, + Post => DMA_Receive_Requests_Enabled (This); + + procedure Disable_DMA_Receive_Requests (This : in out USART) with + Inline, + Post => not DMA_Receive_Requests_Enabled (This); + + function DMA_Receive_Requests_Enabled (This : USART) return Boolean with + Inline; + + procedure Pause_DMA_Transmission (This : in out USART) + renames Disable_DMA_Transmit_Requests; + + procedure Resume_DMA_Transmission (This : in out USART) with + Inline, + Post => DMA_Transmit_Requests_Enabled (This) and + Enabled (This); + + procedure Pause_DMA_Reception (This : in out USART) + renames Disable_DMA_Receive_Requests; + + procedure Resume_DMA_Reception (This : in out USART) with + Inline, + Post => DMA_Receive_Requests_Enabled (This) and + Enabled (This); + + function Data_Register_Address (This : USART) return System.Address with + Inline; + -- Returns the address of the USART Data Register. This is exported + -- STRICTLY for the sake of clients driving a USART via DMA. All other + -- clients of this package should use the procedural interfaces Transmit + -- and Receive instead of directly accessing the Data Register! + -- Seriously, don't use this function otherwise. + + ----------------------------- + -- HAL.UART implementation -- + ----------------------------- + + overriding + function Data_Size (This : USART) return HAL.UART.UART_Data_Size; + + overriding + procedure Transmit + (This : in out USART; + Data : UART_Data_8b; + Status : out UART_Status; + Timeout : Natural := 1000) + with + Pre'Class => Data_Size (This) = Data_Size_8b; + + overriding + procedure Transmit + (This : in out USART; + Data : UART_Data_9b; + Status : out UART_Status; + Timeout : Natural := 1000) + with + Pre'Class => Data_Size (This) = Data_Size_9b; + + overriding + procedure Receive + (This : in out USART; + Data : out UART_Data_8b; + Status : out UART_Status; + Timeout : Natural := 1000) + with + Pre'Class => Data_Size (This) = Data_Size_8b; + + overriding + procedure Receive + (This : in out USART; + Data : out UART_Data_9b; + Status : out UART_Status; + Timeout : Natural := 1000) + with + Pre'Class => Data_Size (This) = Data_Size_9b; + +private + + function APB_Clock (This : USART) return UInt32 with Inline; + -- Returns either APB1 or APB2 clock rate, in Hertz, depending on the + -- USART. For the sake of not making this package board-specific, we assume + -- that we are given a valid USART object at a valid address, AND that the + -- USART devices really are configured such that only 1 and 6 are on APB2. + -- Therefore, if a board has additional USARTs beyond USART6, eg USART8 on + -- the F429I Discovery board, they better conform to that assumption. + -- See Note # 2 in each of Tables 139-141 of the RM on pages 970 - 972. + + type Internal_USART is new STM32_SVD.USART.USART_Peripheral; + + type USART (Periph : not null access Internal_USART) is + limited new HAL.UART.UART_Port with null record; + +end STM32.USARTs; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-adc.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-adc.ads new file mode 100644 index 000000000..874ed5d72 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-adc.ads @@ -0,0 +1,693 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.ADC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- status register + type SR_Register is record + -- Analog watchdog flag + AWD : Boolean := False; + -- Regular channel end of conversion + EOC : Boolean := False; + -- Injected channel end of conversion + JEOC : Boolean := False; + -- Injected channel start flag + JSTRT : Boolean := False; + -- Regular channel start flag + STRT : Boolean := False; + -- Overrun + OVR : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + AWD at 0 range 0 .. 0; + EOC at 0 range 1 .. 1; + JEOC at 0 range 2 .. 2; + JSTRT at 0 range 3 .. 3; + STRT at 0 range 4 .. 4; + OVR at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CR1_AWDCH_Field is HAL.UInt5; + subtype CR1_DISCNUM_Field is HAL.UInt3; + subtype CR1_RES_Field is HAL.UInt2; + + -- control register 1 + type CR1_Register is record + -- Analog watchdog channel select bits + AWDCH : CR1_AWDCH_Field := 16#0#; + -- Interrupt enable for EOC + EOCIE : Boolean := False; + -- Analog watchdog interrupt enable + AWDIE : Boolean := False; + -- Interrupt enable for injected channels + JEOCIE : Boolean := False; + -- Scan mode + SCAN : Boolean := False; + -- Enable the watchdog on a single channel in scan mode + AWDSGL : Boolean := False; + -- Automatic injected group conversion + JAUTO : Boolean := False; + -- Discontinuous mode on regular channels + DISCEN : Boolean := False; + -- Discontinuous mode on injected channels + JDISCEN : Boolean := False; + -- Discontinuous mode channel count + DISCNUM : CR1_DISCNUM_Field := 16#0#; + -- unspecified + Reserved_16_21 : HAL.UInt6 := 16#0#; + -- Analog watchdog enable on injected channels + JAWDEN : Boolean := False; + -- Analog watchdog enable on regular channels + AWDEN : Boolean := False; + -- Resolution + RES : CR1_RES_Field := 16#0#; + -- Overrun interrupt enable + OVRIE : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register use record + AWDCH at 0 range 0 .. 4; + EOCIE at 0 range 5 .. 5; + AWDIE at 0 range 6 .. 6; + JEOCIE at 0 range 7 .. 7; + SCAN at 0 range 8 .. 8; + AWDSGL at 0 range 9 .. 9; + JAUTO at 0 range 10 .. 10; + DISCEN at 0 range 11 .. 11; + JDISCEN at 0 range 12 .. 12; + DISCNUM at 0 range 13 .. 15; + Reserved_16_21 at 0 range 16 .. 21; + JAWDEN at 0 range 22 .. 22; + AWDEN at 0 range 23 .. 23; + RES at 0 range 24 .. 25; + OVRIE at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype CR2_JEXTSEL_Field is HAL.UInt4; + subtype CR2_JEXTEN_Field is HAL.UInt2; + subtype CR2_EXTSEL_Field is HAL.UInt4; + subtype CR2_EXTEN_Field is HAL.UInt2; + + -- control register 2 + type CR2_Register is record + -- A/D Converter ON / OFF + ADON : Boolean := False; + -- Continuous conversion + CONT : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Direct memory access mode (for single ADC mode) + DMA : Boolean := False; + -- DMA disable selection (for single ADC mode) + DDS : Boolean := False; + -- End of conversion selection + EOCS : Boolean := False; + -- Data alignment + ALIGN : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- External event select for injected group + JEXTSEL : CR2_JEXTSEL_Field := 16#0#; + -- External trigger enable for injected channels + JEXTEN : CR2_JEXTEN_Field := 16#0#; + -- Start conversion of injected channels + JSWSTART : Boolean := False; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- External event select for regular group + EXTSEL : CR2_EXTSEL_Field := 16#0#; + -- External trigger enable for regular channels + EXTEN : CR2_EXTEN_Field := 16#0#; + -- Start conversion of regular channels + SWSTART : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register use record + ADON at 0 range 0 .. 0; + CONT at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + DMA at 0 range 8 .. 8; + DDS at 0 range 9 .. 9; + EOCS at 0 range 10 .. 10; + ALIGN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + JEXTSEL at 0 range 16 .. 19; + JEXTEN at 0 range 20 .. 21; + JSWSTART at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + EXTSEL at 0 range 24 .. 27; + EXTEN at 0 range 28 .. 29; + SWSTART at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype JOFR1_JOFFSET1_Field is HAL.UInt12; + + -- injected channel data offset register x + type JOFR1_Register is record + -- Data offset for injected channel x + JOFFSET1 : JOFR1_JOFFSET1_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JOFR1_Register use record + JOFFSET1 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR2_JOFFSET2_Field is HAL.UInt12; + + -- injected channel data offset register x + type JOFR2_Register is record + -- Data offset for injected channel x + JOFFSET2 : JOFR2_JOFFSET2_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JOFR2_Register use record + JOFFSET2 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR3_JOFFSET3_Field is HAL.UInt12; + + -- injected channel data offset register x + type JOFR3_Register is record + -- Data offset for injected channel x + JOFFSET3 : JOFR3_JOFFSET3_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JOFR3_Register use record + JOFFSET3 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR4_JOFFSET4_Field is HAL.UInt12; + + -- injected channel data offset register x + type JOFR4_Register is record + -- Data offset for injected channel x + JOFFSET4 : JOFR4_JOFFSET4_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JOFR4_Register use record + JOFFSET4 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype HTR_HT_Field is HAL.UInt12; + + -- watchdog higher threshold register + type HTR_Register is record + -- Analog watchdog higher threshold + HT : HTR_HT_Field := 16#FFF#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HTR_Register use record + HT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype LTR_LT_Field is HAL.UInt12; + + -- watchdog lower threshold register + type LTR_Register is record + -- Analog watchdog lower threshold + LT : LTR_LT_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LTR_Register use record + LT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- SQR1_SQ array element + subtype SQR1_SQ_Element is HAL.UInt5; + + -- SQR1_SQ array + type SQR1_SQ_Field_Array is array (13 .. 16) of SQR1_SQ_Element + with Component_Size => 5, Size => 20; + + -- Type definition for SQR1_SQ + type SQR1_SQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SQ as a value + Val : HAL.UInt20; + when True => + -- SQ as an array + Arr : SQR1_SQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 20; + + for SQR1_SQ_Field use record + Val at 0 range 0 .. 19; + Arr at 0 range 0 .. 19; + end record; + + subtype SQR1_L_Field is HAL.UInt4; + + -- regular sequence register 1 + type SQR1_Register is record + -- 13th conversion in regular sequence + SQ : SQR1_SQ_Field := (As_Array => False, Val => 16#0#); + -- Regular channel sequence length + L : SQR1_L_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SQR1_Register use record + SQ at 0 range 0 .. 19; + L at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- SQR2_SQ array element + subtype SQR2_SQ_Element is HAL.UInt5; + + -- SQR2_SQ array + type SQR2_SQ_Field_Array is array (7 .. 12) of SQR2_SQ_Element + with Component_Size => 5, Size => 30; + + -- Type definition for SQR2_SQ + type SQR2_SQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SQ as a value + Val : HAL.UInt30; + when True => + -- SQ as an array + Arr : SQR2_SQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 30; + + for SQR2_SQ_Field use record + Val at 0 range 0 .. 29; + Arr at 0 range 0 .. 29; + end record; + + -- regular sequence register 2 + type SQR2_Register is record + -- 7th conversion in regular sequence + SQ : SQR2_SQ_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SQR2_Register use record + SQ at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- SQR3_SQ array element + subtype SQR3_SQ_Element is HAL.UInt5; + + -- SQR3_SQ array + type SQR3_SQ_Field_Array is array (1 .. 6) of SQR3_SQ_Element + with Component_Size => 5, Size => 30; + + -- Type definition for SQR3_SQ + type SQR3_SQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SQ as a value + Val : HAL.UInt30; + when True => + -- SQ as an array + Arr : SQR3_SQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 30; + + for SQR3_SQ_Field use record + Val at 0 range 0 .. 29; + Arr at 0 range 0 .. 29; + end record; + + -- regular sequence register 3 + type SQR3_Register is record + -- 1st conversion in regular sequence + SQ : SQR3_SQ_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SQR3_Register use record + SQ at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- JSQR_JSQ array element + subtype JSQR_JSQ_Element is HAL.UInt5; + + -- JSQR_JSQ array + type JSQR_JSQ_Field_Array is array (1 .. 4) of JSQR_JSQ_Element + with Component_Size => 5, Size => 20; + + -- Type definition for JSQR_JSQ + type JSQR_JSQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- JSQ as a value + Val : HAL.UInt20; + when True => + -- JSQ as an array + Arr : JSQR_JSQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 20; + + for JSQR_JSQ_Field use record + Val at 0 range 0 .. 19; + Arr at 0 range 0 .. 19; + end record; + + subtype JSQR_JL_Field is HAL.UInt2; + + -- injected sequence register + type JSQR_Register is record + -- 1st conversion in injected sequence + JSQ : JSQR_JSQ_Field := (As_Array => False, Val => 16#0#); + -- Injected sequence length + JL : JSQR_JL_Field := 16#0#; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JSQR_Register use record + JSQ at 0 range 0 .. 19; + JL at 0 range 20 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype JDR_JDATA_Field is HAL.UInt16; + + -- injected data register x + type JDR_Register is record + -- Read-only. Injected data + JDATA : JDR_JDATA_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for JDR_Register use record + JDATA at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DR_DATA_Field is HAL.UInt16; + + -- regular data register + type DR_Register is record + -- Read-only. Regular data + DATA : DR_DATA_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DR_Register use record + DATA at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- ADC Common status register + type CSR_Register is record + -- Read-only. Analog watchdog flag of ADC 1 + AWD1 : Boolean; + -- Read-only. End of conversion of ADC 1 + EOC1 : Boolean; + -- Read-only. Injected channel end of conversion of ADC 1 + JEOC1 : Boolean; + -- Read-only. Injected channel Start flag of ADC 1 + JSTRT1 : Boolean; + -- Read-only. Regular channel Start flag of ADC 1 + STRT1 : Boolean; + -- Read-only. Overrun flag of ADC 1 + OVR1 : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Analog watchdog flag of ADC 2 + AWD2 : Boolean; + -- Read-only. End of conversion of ADC 2 + EOC2 : Boolean; + -- Read-only. Injected channel end of conversion of ADC 2 + JEOC2 : Boolean; + -- Read-only. Injected channel Start flag of ADC 2 + JSTRT2 : Boolean; + -- Read-only. Regular channel Start flag of ADC 2 + STRT2 : Boolean; + -- Read-only. Overrun flag of ADC 2 + OVR2 : Boolean; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Analog watchdog flag of ADC 3 + AWD3 : Boolean; + -- Read-only. End of conversion of ADC 3 + EOC3 : Boolean; + -- Read-only. Injected channel end of conversion of ADC 3 + JEOC3 : Boolean; + -- Read-only. Injected channel Start flag of ADC 3 + JSTRT3 : Boolean; + -- Read-only. Regular channel Start flag of ADC 3 + STRT3 : Boolean; + -- Read-only. Overrun flag of ADC3 + OVR3 : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSR_Register use record + AWD1 at 0 range 0 .. 0; + EOC1 at 0 range 1 .. 1; + JEOC1 at 0 range 2 .. 2; + JSTRT1 at 0 range 3 .. 3; + STRT1 at 0 range 4 .. 4; + OVR1 at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + AWD2 at 0 range 8 .. 8; + EOC2 at 0 range 9 .. 9; + JEOC2 at 0 range 10 .. 10; + JSTRT2 at 0 range 11 .. 11; + STRT2 at 0 range 12 .. 12; + OVR2 at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + AWD3 at 0 range 16 .. 16; + EOC3 at 0 range 17 .. 17; + JEOC3 at 0 range 18 .. 18; + JSTRT3 at 0 range 19 .. 19; + STRT3 at 0 range 20 .. 20; + OVR3 at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype CCR_DELAY_Field is HAL.UInt4; + subtype CCR_DMA_Field is HAL.UInt2; + subtype CCR_ADCPRE_Field is HAL.UInt2; + + -- ADC common control register + type CCR_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Delay between 2 sampling phases + DELAY_k : CCR_DELAY_Field := 16#0#; + -- unspecified + Reserved_12_12 : HAL.Bit := 16#0#; + -- DMA disable selection for multi-ADC mode + DDS : Boolean := False; + -- Direct memory access mode for multi ADC mode + DMA : CCR_DMA_Field := 16#0#; + -- ADC prescaler + ADCPRE : CCR_ADCPRE_Field := 16#0#; + -- unspecified + Reserved_18_21 : HAL.UInt4 := 16#0#; + -- VBAT enable + VBATE : Boolean := False; + -- Temperature sensor and VREFINT enable + TSVREFE : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR_Register use record + Reserved_0_7 at 0 range 0 .. 7; + DELAY_k at 0 range 8 .. 11; + Reserved_12_12 at 0 range 12 .. 12; + DDS at 0 range 13 .. 13; + DMA at 0 range 14 .. 15; + ADCPRE at 0 range 16 .. 17; + Reserved_18_21 at 0 range 18 .. 21; + VBATE at 0 range 22 .. 22; + TSVREFE at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Analog-to-digital converter + type ADC1_Peripheral is record + -- status register + SR : aliased SR_Register; + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register; + -- sample time register 1 + SMPR1 : aliased HAL.UInt32; + -- sample time register 2 + SMPR2 : aliased HAL.UInt32; + -- injected channel data offset register x + JOFR1 : aliased JOFR1_Register; + -- injected channel data offset register x + JOFR2 : aliased JOFR2_Register; + -- injected channel data offset register x + JOFR3 : aliased JOFR3_Register; + -- injected channel data offset register x + JOFR4 : aliased JOFR4_Register; + -- watchdog higher threshold register + HTR : aliased HTR_Register; + -- watchdog lower threshold register + LTR : aliased LTR_Register; + -- regular sequence register 1 + SQR1 : aliased SQR1_Register; + -- regular sequence register 2 + SQR2 : aliased SQR2_Register; + -- regular sequence register 3 + SQR3 : aliased SQR3_Register; + -- injected sequence register + JSQR : aliased JSQR_Register; + -- injected data register x + JDR1 : aliased JDR_Register; + -- injected data register x + JDR2 : aliased JDR_Register; + -- injected data register x + JDR3 : aliased JDR_Register; + -- injected data register x + JDR4 : aliased JDR_Register; + -- regular data register + DR : aliased DR_Register; + end record + with Volatile; + + for ADC1_Peripheral use record + SR at 16#0# range 0 .. 31; + CR1 at 16#4# range 0 .. 31; + CR2 at 16#8# range 0 .. 31; + SMPR1 at 16#C# range 0 .. 31; + SMPR2 at 16#10# range 0 .. 31; + JOFR1 at 16#14# range 0 .. 31; + JOFR2 at 16#18# range 0 .. 31; + JOFR3 at 16#1C# range 0 .. 31; + JOFR4 at 16#20# range 0 .. 31; + HTR at 16#24# range 0 .. 31; + LTR at 16#28# range 0 .. 31; + SQR1 at 16#2C# range 0 .. 31; + SQR2 at 16#30# range 0 .. 31; + SQR3 at 16#34# range 0 .. 31; + JSQR at 16#38# range 0 .. 31; + JDR1 at 16#3C# range 0 .. 31; + JDR2 at 16#40# range 0 .. 31; + JDR3 at 16#44# range 0 .. 31; + JDR4 at 16#48# range 0 .. 31; + DR at 16#4C# range 0 .. 31; + end record; + + -- Analog-to-digital converter + ADC1_Periph : aliased ADC1_Peripheral + with Import, Address => ADC1_Base; + + -- ADC common registers + type ADC_Common_Peripheral is record + -- ADC Common status register + CSR : aliased CSR_Register; + -- ADC common control register + CCR : aliased CCR_Register; + end record + with Volatile; + + for ADC_Common_Peripheral use record + CSR at 16#0# range 0 .. 31; + CCR at 16#4# range 0 .. 31; + end record; + + -- ADC common registers + ADC_Common_Periph : aliased ADC_Common_Peripheral + with Import, Address => ADC_Common_Base; + +end STM32_SVD.ADC; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-crc.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-crc.ads new file mode 100644 index 000000000..388e8084b --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-crc.ads @@ -0,0 +1,74 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.CRC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype IDR_IDR_Field is HAL.UInt8; + + -- Independent Data register + type IDR_Register is record + -- Independent Data register + IDR : IDR_IDR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IDR_Register use record + IDR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Control register + type CR_Register is record + -- Write-only. Control regidter + CR : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + CR at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Cryptographic processor + type CRC_Peripheral is record + -- Data register + DR : aliased HAL.UInt32; + -- Independent Data register + IDR : aliased IDR_Register; + -- Control register + CR : aliased CR_Register; + end record + with Volatile; + + for CRC_Peripheral use record + DR at 16#0# range 0 .. 31; + IDR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; + end record; + + -- Cryptographic processor + CRC_Periph : aliased CRC_Peripheral + with Import, Address => CRC_Base; + +end STM32_SVD.CRC; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-dbg.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-dbg.ads new file mode 100644 index 000000000..f6b74cc18 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-dbg.ads @@ -0,0 +1,173 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.DBG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype DBGMCU_IDCODE_DEV_ID_Field is HAL.UInt12; + subtype DBGMCU_IDCODE_REV_ID_Field is HAL.UInt16; + + -- IDCODE + type DBGMCU_IDCODE_Register is record + -- Read-only. DEV_ID + DEV_ID : DBGMCU_IDCODE_DEV_ID_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. REV_ID + REV_ID : DBGMCU_IDCODE_REV_ID_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGMCU_IDCODE_Register use record + DEV_ID at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + REV_ID at 0 range 16 .. 31; + end record; + + subtype DBGMCU_CR_TRACE_MODE_Field is HAL.UInt2; + + -- Control Register + type DBGMCU_CR_Register is record + -- DBG_SLEEP + DBG_SLEEP : Boolean := False; + -- DBG_STOP + DBG_STOP : Boolean := False; + -- DBG_STANDBY + DBG_STANDBY : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- TRACE_IOEN + TRACE_IOEN : Boolean := False; + -- TRACE_MODE + TRACE_MODE : DBGMCU_CR_TRACE_MODE_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGMCU_CR_Register use record + DBG_SLEEP at 0 range 0 .. 0; + DBG_STOP at 0 range 1 .. 1; + DBG_STANDBY at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + TRACE_IOEN at 0 range 5 .. 5; + TRACE_MODE at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Debug MCU APB1 Freeze registe + type DBGMCU_APB1_FZ_Register is record + -- DBG_TIM2_STOP + DBG_TIM2_STOP : Boolean := False; + -- DBG_TIM3 _STOP + DBG_TIM3_STOP : Boolean := False; + -- DBG_TIM4_STOP + DBG_TIM4_STOP : Boolean := False; + -- DBG_TIM5_STOP + DBG_TIM5_STOP : Boolean := False; + -- unspecified + Reserved_4_9 : HAL.UInt6 := 16#0#; + -- RTC stopped when Core is halted + DBG_RTC_Stop : Boolean := False; + -- DBG_WWDG_STOP + DBG_WWDG_STOP : Boolean := False; + -- DBG_IWDEG_STOP + DBG_IWDEG_STOP : Boolean := False; + -- unspecified + Reserved_13_20 : HAL.UInt8 := 16#0#; + -- DBG_J2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT : Boolean := False; + -- DBG_J2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT : Boolean := False; + -- DBG_J2C3SMBUS_TIMEOUT + DBG_I2C3SMBUS_TIMEOUT : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGMCU_APB1_FZ_Register use record + DBG_TIM2_STOP at 0 range 0 .. 0; + DBG_TIM3_STOP at 0 range 1 .. 1; + DBG_TIM4_STOP at 0 range 2 .. 2; + DBG_TIM5_STOP at 0 range 3 .. 3; + Reserved_4_9 at 0 range 4 .. 9; + DBG_RTC_Stop at 0 range 10 .. 10; + DBG_WWDG_STOP at 0 range 11 .. 11; + DBG_IWDEG_STOP at 0 range 12 .. 12; + Reserved_13_20 at 0 range 13 .. 20; + DBG_I2C1_SMBUS_TIMEOUT at 0 range 21 .. 21; + DBG_I2C2_SMBUS_TIMEOUT at 0 range 22 .. 22; + DBG_I2C3SMBUS_TIMEOUT at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Debug MCU APB2 Freeze registe + type DBGMCU_APB2_FZ_Register is record + -- TIM1 counter stopped when core is halted + DBG_TIM1_STOP : Boolean := False; + -- unspecified + Reserved_1_15 : HAL.UInt15 := 16#0#; + -- TIM9 counter stopped when core is halted + DBG_TIM9_STOP : Boolean := False; + -- TIM10 counter stopped when core is halted + DBG_TIM10_STOP : Boolean := False; + -- TIM11 counter stopped when core is halted + DBG_TIM11_STOP : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGMCU_APB2_FZ_Register use record + DBG_TIM1_STOP at 0 range 0 .. 0; + Reserved_1_15 at 0 range 1 .. 15; + DBG_TIM9_STOP at 0 range 16 .. 16; + DBG_TIM10_STOP at 0 range 17 .. 17; + DBG_TIM11_STOP at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Debug support + type DBG_Peripheral is record + -- IDCODE + DBGMCU_IDCODE : aliased DBGMCU_IDCODE_Register; + -- Control Register + DBGMCU_CR : aliased DBGMCU_CR_Register; + -- Debug MCU APB1 Freeze registe + DBGMCU_APB1_FZ : aliased DBGMCU_APB1_FZ_Register; + -- Debug MCU APB2 Freeze registe + DBGMCU_APB2_FZ : aliased DBGMCU_APB2_FZ_Register; + end record + with Volatile; + + for DBG_Peripheral use record + DBGMCU_IDCODE at 16#0# range 0 .. 31; + DBGMCU_CR at 16#4# range 0 .. 31; + DBGMCU_APB1_FZ at 16#8# range 0 .. 31; + DBGMCU_APB2_FZ at 16#C# range 0 .. 31; + end record; + + -- Debug support + DBG_Periph : aliased DBG_Peripheral + with Import, Address => DBG_Base; + +end STM32_SVD.DBG; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-dma.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-dma.ads new file mode 100644 index 000000000..5a8e2363f --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-dma.ads @@ -0,0 +1,1573 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.DMA is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- low interrupt status register + type LISR_Register is record + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) + FEIF0 : Boolean; + -- unspecified + Reserved_1_1 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) + DMEIF0 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=3..0) + TEIF0 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=3..0) + HTIF0 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) + TCIF0 : Boolean; + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) + FEIF1 : Boolean; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) + DMEIF1 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=3..0) + TEIF1 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=3..0) + HTIF1 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) + TCIF1 : Boolean; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) + FEIF2 : Boolean; + -- unspecified + Reserved_17_17 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) + DMEIF2 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=3..0) + TEIF2 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=3..0) + HTIF2 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) + TCIF2 : Boolean; + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) + FEIF3 : Boolean; + -- unspecified + Reserved_23_23 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) + DMEIF3 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=3..0) + TEIF3 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=3..0) + HTIF3 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) + TCIF3 : Boolean; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LISR_Register use record + FEIF0 at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DMEIF0 at 0 range 2 .. 2; + TEIF0 at 0 range 3 .. 3; + HTIF0 at 0 range 4 .. 4; + TCIF0 at 0 range 5 .. 5; + FEIF1 at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DMEIF1 at 0 range 8 .. 8; + TEIF1 at 0 range 9 .. 9; + HTIF1 at 0 range 10 .. 10; + TCIF1 at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FEIF2 at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + DMEIF2 at 0 range 18 .. 18; + TEIF2 at 0 range 19 .. 19; + HTIF2 at 0 range 20 .. 20; + TCIF2 at 0 range 21 .. 21; + FEIF3 at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + DMEIF3 at 0 range 24 .. 24; + TEIF3 at 0 range 25 .. 25; + HTIF3 at 0 range 26 .. 26; + TCIF3 at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- high interrupt status register + type HISR_Register is record + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) + FEIF4 : Boolean; + -- unspecified + Reserved_1_1 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) + DMEIF4 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=7..4) + TEIF4 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=7..4) + HTIF4 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) + TCIF4 : Boolean; + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) + FEIF5 : Boolean; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) + DMEIF5 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=7..4) + TEIF5 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=7..4) + HTIF5 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) + TCIF5 : Boolean; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) + FEIF6 : Boolean; + -- unspecified + Reserved_17_17 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) + DMEIF6 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=7..4) + TEIF6 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=7..4) + HTIF6 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) + TCIF6 : Boolean; + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) + FEIF7 : Boolean; + -- unspecified + Reserved_23_23 : HAL.Bit; + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) + DMEIF7 : Boolean; + -- Read-only. Stream x transfer error interrupt flag (x=7..4) + TEIF7 : Boolean; + -- Read-only. Stream x half transfer interrupt flag (x=7..4) + HTIF7 : Boolean; + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) + TCIF7 : Boolean; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HISR_Register use record + FEIF4 at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DMEIF4 at 0 range 2 .. 2; + TEIF4 at 0 range 3 .. 3; + HTIF4 at 0 range 4 .. 4; + TCIF4 at 0 range 5 .. 5; + FEIF5 at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DMEIF5 at 0 range 8 .. 8; + TEIF5 at 0 range 9 .. 9; + HTIF5 at 0 range 10 .. 10; + TCIF5 at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FEIF6 at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + DMEIF6 at 0 range 18 .. 18; + TEIF6 at 0 range 19 .. 19; + HTIF6 at 0 range 20 .. 20; + TCIF6 at 0 range 21 .. 21; + FEIF7 at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + DMEIF7 at 0 range 24 .. 24; + TEIF7 at 0 range 25 .. 25; + HTIF7 at 0 range 26 .. 26; + TCIF7 at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- low interrupt flag clear register + type LIFCR_Register is record + -- Write-only. Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF0 : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 3..0) + CDMEIF0 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF0 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF0 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 3..0) + CTCIF0 : Boolean := False; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF1 : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 3..0) + CDMEIF1 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF1 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF1 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 3..0) + CTCIF1 : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF2 : Boolean := False; + -- unspecified + Reserved_17_17 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 3..0) + CDMEIF2 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF2 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF2 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 3..0) + CTCIF2 : Boolean := False; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF3 : Boolean := False; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 3..0) + CDMEIF3 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF3 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF3 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 3..0) + CTCIF3 : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIFCR_Register use record + CFEIF0 at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + CDMEIF0 at 0 range 2 .. 2; + CTEIF0 at 0 range 3 .. 3; + CHTIF0 at 0 range 4 .. 4; + CTCIF0 at 0 range 5 .. 5; + CFEIF1 at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CDMEIF1 at 0 range 8 .. 8; + CTEIF1 at 0 range 9 .. 9; + CHTIF1 at 0 range 10 .. 10; + CTCIF1 at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CFEIF2 at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + CDMEIF2 at 0 range 18 .. 18; + CTEIF2 at 0 range 19 .. 19; + CHTIF2 at 0 range 20 .. 20; + CTCIF2 at 0 range 21 .. 21; + CFEIF3 at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + CDMEIF3 at 0 range 24 .. 24; + CTEIF3 at 0 range 25 .. 25; + CHTIF3 at 0 range 26 .. 26; + CTCIF3 at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- high interrupt flag clear register + type HIFCR_Register is record + -- Write-only. Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF4 : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 7..4) + CDMEIF4 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF4 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF4 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 7..4) + CTCIF4 : Boolean := False; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF5 : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 7..4) + CDMEIF5 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF5 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF5 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 7..4) + CTCIF5 : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF6 : Boolean := False; + -- unspecified + Reserved_17_17 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 7..4) + CDMEIF6 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF6 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF6 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 7..4) + CTCIF6 : Boolean := False; + -- Write-only. Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF7 : Boolean := False; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Write-only. Stream x clear direct mode error interrupt flag (x = + -- 7..4) + CDMEIF7 : Boolean := False; + -- Write-only. Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF7 : Boolean := False; + -- Write-only. Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF7 : Boolean := False; + -- Write-only. Stream x clear transfer complete interrupt flag (x = + -- 7..4) + CTCIF7 : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HIFCR_Register use record + CFEIF4 at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + CDMEIF4 at 0 range 2 .. 2; + CTEIF4 at 0 range 3 .. 3; + CHTIF4 at 0 range 4 .. 4; + CTCIF4 at 0 range 5 .. 5; + CFEIF5 at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CDMEIF5 at 0 range 8 .. 8; + CTEIF5 at 0 range 9 .. 9; + CHTIF5 at 0 range 10 .. 10; + CTCIF5 at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CFEIF6 at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + CDMEIF6 at 0 range 18 .. 18; + CTEIF6 at 0 range 19 .. 19; + CHTIF6 at 0 range 20 .. 20; + CTCIF6 at 0 range 21 .. 21; + CFEIF7 at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + CDMEIF7 at 0 range 24 .. 24; + CTEIF7 at 0 range 25 .. 25; + CHTIF7 at 0 range 26 .. 26; + CTCIF7 at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S0CR_DIR_Field is HAL.UInt2; + subtype S0CR_PSIZE_Field is HAL.UInt2; + subtype S0CR_MSIZE_Field is HAL.UInt2; + subtype S0CR_PL_Field is HAL.UInt2; + subtype S0CR_PBURST_Field is HAL.UInt2; + subtype S0CR_MBURST_Field is HAL.UInt2; + subtype S0CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S0CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S0CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S0CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S0CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S0CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- Peripheral burst transfer configuration + PBURST : S0CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S0CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S0CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S0CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S0NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S0NDTR_Register is record + -- Number of data items to transfer + NDT : S0NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S0NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S0FCR_FTH_Field is HAL.UInt2; + subtype S0FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S0FCR_Register is record + -- FIFO threshold selection + FTH : S0FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S0FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S0FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S1CR_DIR_Field is HAL.UInt2; + subtype S1CR_PSIZE_Field is HAL.UInt2; + subtype S1CR_MSIZE_Field is HAL.UInt2; + subtype S1CR_PL_Field is HAL.UInt2; + subtype S1CR_PBURST_Field is HAL.UInt2; + subtype S1CR_MBURST_Field is HAL.UInt2; + subtype S1CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S1CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S1CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S1CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S1CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S1CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S1CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S1CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S1CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S1CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S1NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S1NDTR_Register is record + -- Number of data items to transfer + NDT : S1NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S1NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S1FCR_FTH_Field is HAL.UInt2; + subtype S1FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S1FCR_Register is record + -- FIFO threshold selection + FTH : S1FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S1FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S1FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S2CR_DIR_Field is HAL.UInt2; + subtype S2CR_PSIZE_Field is HAL.UInt2; + subtype S2CR_MSIZE_Field is HAL.UInt2; + subtype S2CR_PL_Field is HAL.UInt2; + subtype S2CR_PBURST_Field is HAL.UInt2; + subtype S2CR_MBURST_Field is HAL.UInt2; + subtype S2CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S2CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S2CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S2CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S2CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S2CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S2CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S2CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S2CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S2CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S2NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S2NDTR_Register is record + -- Number of data items to transfer + NDT : S2NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S2NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S2FCR_FTH_Field is HAL.UInt2; + subtype S2FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S2FCR_Register is record + -- FIFO threshold selection + FTH : S2FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S2FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S2FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S3CR_DIR_Field is HAL.UInt2; + subtype S3CR_PSIZE_Field is HAL.UInt2; + subtype S3CR_MSIZE_Field is HAL.UInt2; + subtype S3CR_PL_Field is HAL.UInt2; + subtype S3CR_PBURST_Field is HAL.UInt2; + subtype S3CR_MBURST_Field is HAL.UInt2; + subtype S3CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S3CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S3CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S3CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S3CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S3CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S3CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S3CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S3CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S3CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S3NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S3NDTR_Register is record + -- Number of data items to transfer + NDT : S3NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S3NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S3FCR_FTH_Field is HAL.UInt2; + subtype S3FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S3FCR_Register is record + -- FIFO threshold selection + FTH : S3FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S3FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S3FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S4CR_DIR_Field is HAL.UInt2; + subtype S4CR_PSIZE_Field is HAL.UInt2; + subtype S4CR_MSIZE_Field is HAL.UInt2; + subtype S4CR_PL_Field is HAL.UInt2; + subtype S4CR_PBURST_Field is HAL.UInt2; + subtype S4CR_MBURST_Field is HAL.UInt2; + subtype S4CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S4CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S4CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S4CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S4CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S4CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S4CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S4CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S4CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S4CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S4NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S4NDTR_Register is record + -- Number of data items to transfer + NDT : S4NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S4NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S4FCR_FTH_Field is HAL.UInt2; + subtype S4FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S4FCR_Register is record + -- FIFO threshold selection + FTH : S4FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S4FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S4FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S5CR_DIR_Field is HAL.UInt2; + subtype S5CR_PSIZE_Field is HAL.UInt2; + subtype S5CR_MSIZE_Field is HAL.UInt2; + subtype S5CR_PL_Field is HAL.UInt2; + subtype S5CR_PBURST_Field is HAL.UInt2; + subtype S5CR_MBURST_Field is HAL.UInt2; + subtype S5CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S5CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S5CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S5CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S5CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S5CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S5CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S5CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S5CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S5CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S5NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S5NDTR_Register is record + -- Number of data items to transfer + NDT : S5NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S5NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S5FCR_FTH_Field is HAL.UInt2; + subtype S5FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S5FCR_Register is record + -- FIFO threshold selection + FTH : S5FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S5FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S5FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S6CR_DIR_Field is HAL.UInt2; + subtype S6CR_PSIZE_Field is HAL.UInt2; + subtype S6CR_MSIZE_Field is HAL.UInt2; + subtype S6CR_PL_Field is HAL.UInt2; + subtype S6CR_PBURST_Field is HAL.UInt2; + subtype S6CR_MBURST_Field is HAL.UInt2; + subtype S6CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S6CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S6CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S6CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S6CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S6CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S6CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S6CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S6CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S6CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S6NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S6NDTR_Register is record + -- Number of data items to transfer + NDT : S6NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S6NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S6FCR_FTH_Field is HAL.UInt2; + subtype S6FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S6FCR_Register is record + -- FIFO threshold selection + FTH : S6FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S6FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S6FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype S7CR_DIR_Field is HAL.UInt2; + subtype S7CR_PSIZE_Field is HAL.UInt2; + subtype S7CR_MSIZE_Field is HAL.UInt2; + subtype S7CR_PL_Field is HAL.UInt2; + subtype S7CR_PBURST_Field is HAL.UInt2; + subtype S7CR_MBURST_Field is HAL.UInt2; + subtype S7CR_CHSEL_Field is HAL.UInt3; + + -- stream x configuration register + type S7CR_Register is record + -- Stream enable / flag stream ready when read low + EN : Boolean := False; + -- Direct mode error interrupt enable + DMEIE : Boolean := False; + -- Transfer error interrupt enable + TEIE : Boolean := False; + -- Half transfer interrupt enable + HTIE : Boolean := False; + -- Transfer complete interrupt enable + TCIE : Boolean := False; + -- Peripheral flow controller + PFCTRL : Boolean := False; + -- Data transfer direction + DIR : S7CR_DIR_Field := 16#0#; + -- Circular mode + CIRC : Boolean := False; + -- Peripheral increment mode + PINC : Boolean := False; + -- Memory increment mode + MINC : Boolean := False; + -- Peripheral data size + PSIZE : S7CR_PSIZE_Field := 16#0#; + -- Memory data size + MSIZE : S7CR_MSIZE_Field := 16#0#; + -- Peripheral increment offset size + PINCOS : Boolean := False; + -- Priority level + PL : S7CR_PL_Field := 16#0#; + -- Double buffer mode + DBM : Boolean := False; + -- Current target (only in double buffer mode) + CT : Boolean := False; + -- ACK + ACK : Boolean := False; + -- Peripheral burst transfer configuration + PBURST : S7CR_PBURST_Field := 16#0#; + -- Memory burst transfer configuration + MBURST : S7CR_MBURST_Field := 16#0#; + -- Channel selection + CHSEL : S7CR_CHSEL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S7CR_Register use record + EN at 0 range 0 .. 0; + DMEIE at 0 range 1 .. 1; + TEIE at 0 range 2 .. 2; + HTIE at 0 range 3 .. 3; + TCIE at 0 range 4 .. 4; + PFCTRL at 0 range 5 .. 5; + DIR at 0 range 6 .. 7; + CIRC at 0 range 8 .. 8; + PINC at 0 range 9 .. 9; + MINC at 0 range 10 .. 10; + PSIZE at 0 range 11 .. 12; + MSIZE at 0 range 13 .. 14; + PINCOS at 0 range 15 .. 15; + PL at 0 range 16 .. 17; + DBM at 0 range 18 .. 18; + CT at 0 range 19 .. 19; + ACK at 0 range 20 .. 20; + PBURST at 0 range 21 .. 22; + MBURST at 0 range 23 .. 24; + CHSEL at 0 range 25 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype S7NDTR_NDT_Field is HAL.UInt16; + + -- stream x number of data register + type S7NDTR_Register is record + -- Number of data items to transfer + NDT : S7NDTR_NDT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S7NDTR_Register use record + NDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype S7FCR_FTH_Field is HAL.UInt2; + subtype S7FCR_FS_Field is HAL.UInt3; + + -- stream x FIFO control register + type S7FCR_Register is record + -- FIFO threshold selection + FTH : S7FCR_FTH_Field := 16#1#; + -- Direct mode disable + DMDIS : Boolean := False; + -- Read-only. FIFO status + FS : S7FCR_FS_Field := 16#4#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- FIFO error interrupt enable + FEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for S7FCR_Register use record + FTH at 0 range 0 .. 1; + DMDIS at 0 range 2 .. 2; + FS at 0 range 3 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + FEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- DMA controller + type DMA_Peripheral is record + -- low interrupt status register + LISR : aliased LISR_Register; + -- high interrupt status register + HISR : aliased HISR_Register; + -- low interrupt flag clear register + LIFCR : aliased LIFCR_Register; + -- high interrupt flag clear register + HIFCR : aliased HIFCR_Register; + -- stream x configuration register + S0CR : aliased S0CR_Register; + -- stream x number of data register + S0NDTR : aliased S0NDTR_Register; + -- stream x peripheral address register + S0PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S0M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S0M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S0FCR : aliased S0FCR_Register; + -- stream x configuration register + S1CR : aliased S1CR_Register; + -- stream x number of data register + S1NDTR : aliased S1NDTR_Register; + -- stream x peripheral address register + S1PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S1M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S1M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S1FCR : aliased S1FCR_Register; + -- stream x configuration register + S2CR : aliased S2CR_Register; + -- stream x number of data register + S2NDTR : aliased S2NDTR_Register; + -- stream x peripheral address register + S2PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S2M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S2M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S2FCR : aliased S2FCR_Register; + -- stream x configuration register + S3CR : aliased S3CR_Register; + -- stream x number of data register + S3NDTR : aliased S3NDTR_Register; + -- stream x peripheral address register + S3PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S3M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S3M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S3FCR : aliased S3FCR_Register; + -- stream x configuration register + S4CR : aliased S4CR_Register; + -- stream x number of data register + S4NDTR : aliased S4NDTR_Register; + -- stream x peripheral address register + S4PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S4M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S4M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S4FCR : aliased S4FCR_Register; + -- stream x configuration register + S5CR : aliased S5CR_Register; + -- stream x number of data register + S5NDTR : aliased S5NDTR_Register; + -- stream x peripheral address register + S5PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S5M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S5M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S5FCR : aliased S5FCR_Register; + -- stream x configuration register + S6CR : aliased S6CR_Register; + -- stream x number of data register + S6NDTR : aliased S6NDTR_Register; + -- stream x peripheral address register + S6PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S6M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S6M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S6FCR : aliased S6FCR_Register; + -- stream x configuration register + S7CR : aliased S7CR_Register; + -- stream x number of data register + S7NDTR : aliased S7NDTR_Register; + -- stream x peripheral address register + S7PAR : aliased HAL.UInt32; + -- stream x memory 0 address register + S7M0AR : aliased HAL.UInt32; + -- stream x memory 1 address register + S7M1AR : aliased HAL.UInt32; + -- stream x FIFO control register + S7FCR : aliased S7FCR_Register; + end record + with Volatile; + + for DMA_Peripheral use record + LISR at 16#0# range 0 .. 31; + HISR at 16#4# range 0 .. 31; + LIFCR at 16#8# range 0 .. 31; + HIFCR at 16#C# range 0 .. 31; + S0CR at 16#10# range 0 .. 31; + S0NDTR at 16#14# range 0 .. 31; + S0PAR at 16#18# range 0 .. 31; + S0M0AR at 16#1C# range 0 .. 31; + S0M1AR at 16#20# range 0 .. 31; + S0FCR at 16#24# range 0 .. 31; + S1CR at 16#28# range 0 .. 31; + S1NDTR at 16#2C# range 0 .. 31; + S1PAR at 16#30# range 0 .. 31; + S1M0AR at 16#34# range 0 .. 31; + S1M1AR at 16#38# range 0 .. 31; + S1FCR at 16#3C# range 0 .. 31; + S2CR at 16#40# range 0 .. 31; + S2NDTR at 16#44# range 0 .. 31; + S2PAR at 16#48# range 0 .. 31; + S2M0AR at 16#4C# range 0 .. 31; + S2M1AR at 16#50# range 0 .. 31; + S2FCR at 16#54# range 0 .. 31; + S3CR at 16#58# range 0 .. 31; + S3NDTR at 16#5C# range 0 .. 31; + S3PAR at 16#60# range 0 .. 31; + S3M0AR at 16#64# range 0 .. 31; + S3M1AR at 16#68# range 0 .. 31; + S3FCR at 16#6C# range 0 .. 31; + S4CR at 16#70# range 0 .. 31; + S4NDTR at 16#74# range 0 .. 31; + S4PAR at 16#78# range 0 .. 31; + S4M0AR at 16#7C# range 0 .. 31; + S4M1AR at 16#80# range 0 .. 31; + S4FCR at 16#84# range 0 .. 31; + S5CR at 16#88# range 0 .. 31; + S5NDTR at 16#8C# range 0 .. 31; + S5PAR at 16#90# range 0 .. 31; + S5M0AR at 16#94# range 0 .. 31; + S5M1AR at 16#98# range 0 .. 31; + S5FCR at 16#9C# range 0 .. 31; + S6CR at 16#A0# range 0 .. 31; + S6NDTR at 16#A4# range 0 .. 31; + S6PAR at 16#A8# range 0 .. 31; + S6M0AR at 16#AC# range 0 .. 31; + S6M1AR at 16#B0# range 0 .. 31; + S6FCR at 16#B4# range 0 .. 31; + S7CR at 16#B8# range 0 .. 31; + S7NDTR at 16#BC# range 0 .. 31; + S7PAR at 16#C0# range 0 .. 31; + S7M0AR at 16#C4# range 0 .. 31; + S7M1AR at 16#C8# range 0 .. 31; + S7FCR at 16#CC# range 0 .. 31; + end record; + + -- DMA controller + DMA1_Periph : aliased DMA_Peripheral + with Import, Address => DMA1_Base; + + -- DMA controller + DMA2_Periph : aliased DMA_Peripheral + with Import, Address => DMA2_Base; + +end STM32_SVD.DMA; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-exti.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-exti.ads new file mode 100644 index 000000000..6af974877 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-exti.ads @@ -0,0 +1,285 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.EXTI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- IMR_MR array + type IMR_MR_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for IMR_MR + type IMR_MR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- MR as a value + Val : HAL.UInt23; + when True => + -- MR as an array + Arr : IMR_MR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for IMR_MR_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Interrupt mask register (EXTI_IMR) + type IMR_Register is record + -- Interrupt Mask on line 0 + MR : IMR_MR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IMR_Register use record + MR at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- EMR_MR array + type EMR_MR_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for EMR_MR + type EMR_MR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- MR as a value + Val : HAL.UInt23; + when True => + -- MR as an array + Arr : EMR_MR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for EMR_MR_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Event mask register (EXTI_EMR) + type EMR_Register is record + -- Event Mask on line 0 + MR : EMR_MR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EMR_Register use record + MR at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- RTSR_TR array + type RTSR_TR_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for RTSR_TR + type RTSR_TR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TR as a value + Val : HAL.UInt23; + when True => + -- TR as an array + Arr : RTSR_TR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for RTSR_TR_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Rising Trigger selection register (EXTI_RTSR) + type RTSR_Register is record + -- Rising trigger event configuration of line 0 + TR : RTSR_TR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RTSR_Register use record + TR at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- FTSR_TR array + type FTSR_TR_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for FTSR_TR + type FTSR_TR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TR as a value + Val : HAL.UInt23; + when True => + -- TR as an array + Arr : FTSR_TR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for FTSR_TR_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Falling Trigger selection register (EXTI_FTSR) + type FTSR_Register is record + -- Falling trigger event configuration of line 0 + TR : FTSR_TR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FTSR_Register use record + TR at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- SWIER array + type SWIER_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for SWIER + type SWIER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SWIER as a value + Val : HAL.UInt23; + when True => + -- SWIER as an array + Arr : SWIER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for SWIER_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Software interrupt event register (EXTI_SWIER) + type SWIER_Register is record + -- Software Interrupt on line 0 + SWIER : SWIER_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SWIER_Register use record + SWIER at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- PR array + type PR_Field_Array is array (0 .. 22) of Boolean + with Component_Size => 1, Size => 23; + + -- Type definition for PR + type PR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PR as a value + Val : HAL.UInt23; + when True => + -- PR as an array + Arr : PR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 23; + + for PR_Field use record + Val at 0 range 0 .. 22; + Arr at 0 range 0 .. 22; + end record; + + -- Pending register (EXTI_PR) + type PR_Register is record + -- Pending bit 0 + PR : PR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PR_Register use record + PR at 0 range 0 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- External interrupt/event controller + type EXTI_Peripheral is record + -- Interrupt mask register (EXTI_IMR) + IMR : aliased IMR_Register; + -- Event mask register (EXTI_EMR) + EMR : aliased EMR_Register; + -- Rising Trigger selection register (EXTI_RTSR) + RTSR : aliased RTSR_Register; + -- Falling Trigger selection register (EXTI_FTSR) + FTSR : aliased FTSR_Register; + -- Software interrupt event register (EXTI_SWIER) + SWIER : aliased SWIER_Register; + -- Pending register (EXTI_PR) + PR : aliased PR_Register; + end record + with Volatile; + + for EXTI_Peripheral use record + IMR at 16#0# range 0 .. 31; + EMR at 16#4# range 0 .. 31; + RTSR at 16#8# range 0 .. 31; + FTSR at 16#C# range 0 .. 31; + SWIER at 16#10# range 0 .. 31; + PR at 16#14# range 0 .. 31; + end record; + + -- External interrupt/event controller + EXTI_Periph : aliased EXTI_Peripheral + with Import, Address => EXTI_Base; + +end STM32_SVD.EXTI; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-flash.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-flash.ads new file mode 100644 index 000000000..6b8ab1e14 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-flash.ads @@ -0,0 +1,219 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.FLASH is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ACR_LATENCY_Field is HAL.UInt3; + + -- Flash access control register + type ACR_Register is record + -- Latency + LATENCY : ACR_LATENCY_Field := 16#0#; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Prefetch enable + PRFTEN : Boolean := False; + -- Instruction cache enable + ICEN : Boolean := False; + -- Data cache enable + DCEN : Boolean := False; + -- Write-only. Instruction cache reset + ICRST : Boolean := False; + -- Data cache reset + DCRST : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACR_Register use record + LATENCY at 0 range 0 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + PRFTEN at 0 range 8 .. 8; + ICEN at 0 range 9 .. 9; + DCEN at 0 range 10 .. 10; + ICRST at 0 range 11 .. 11; + DCRST at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Status register + type SR_Register is record + -- End of operation + EOP : Boolean := False; + -- Operation error + OPERR : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write protection error + WRPERR : Boolean := False; + -- Programming alignment error + PGAERR : Boolean := False; + -- Programming parallelism error + PGPERR : Boolean := False; + -- Programming sequence error + PGSERR : Boolean := False; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Read-only. Busy + BSY : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + EOP at 0 range 0 .. 0; + OPERR at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + WRPERR at 0 range 4 .. 4; + PGAERR at 0 range 5 .. 5; + PGPERR at 0 range 6 .. 6; + PGSERR at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + BSY at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype CR_SNB_Field is HAL.UInt4; + subtype CR_PSIZE_Field is HAL.UInt2; + + -- Control register + type CR_Register is record + -- Programming + PG : Boolean := False; + -- Sector Erase + SER : Boolean := False; + -- Mass Erase + MER : Boolean := False; + -- Sector number + SNB : CR_SNB_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Program size + PSIZE : CR_PSIZE_Field := 16#0#; + -- unspecified + Reserved_10_15 : HAL.UInt6 := 16#0#; + -- Start + STRT : Boolean := False; + -- unspecified + Reserved_17_23 : HAL.UInt7 := 16#0#; + -- End of operation interrupt enable + EOPIE : Boolean := False; + -- Error interrupt enable + ERRIE : Boolean := False; + -- unspecified + Reserved_26_30 : HAL.UInt5 := 16#0#; + -- Lock + LOCK : Boolean := True; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + PG at 0 range 0 .. 0; + SER at 0 range 1 .. 1; + MER at 0 range 2 .. 2; + SNB at 0 range 3 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PSIZE at 0 range 8 .. 9; + Reserved_10_15 at 0 range 10 .. 15; + STRT at 0 range 16 .. 16; + Reserved_17_23 at 0 range 17 .. 23; + EOPIE at 0 range 24 .. 24; + ERRIE at 0 range 25 .. 25; + Reserved_26_30 at 0 range 26 .. 30; + LOCK at 0 range 31 .. 31; + end record; + + subtype OPTCR_BOR_LEV_Field is HAL.UInt2; + subtype OPTCR_RDP_Field is HAL.UInt8; + subtype OPTCR_nWRP_Field is HAL.UInt12; + + -- Flash option control register + type OPTCR_Register is record + -- Option lock + OPTLOCK : Boolean := False; + -- Option start + OPTSTRT : Boolean := False; + -- BOR reset Level + BOR_LEV : OPTCR_BOR_LEV_Field := 16#1#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#1#; + -- WDG_SW User option bytes + WDG_SW : Boolean := False; + -- nRST_STOP User option bytes + nRST_STOP : Boolean := False; + -- nRST_STDBY User option bytes + nRST_STDBY : Boolean := False; + -- Read protect + RDP : OPTCR_RDP_Field := 16#0#; + -- Not write protect + nWRP : OPTCR_nWRP_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OPTCR_Register use record + OPTLOCK at 0 range 0 .. 0; + OPTSTRT at 0 range 1 .. 1; + BOR_LEV at 0 range 2 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + WDG_SW at 0 range 5 .. 5; + nRST_STOP at 0 range 6 .. 6; + nRST_STDBY at 0 range 7 .. 7; + RDP at 0 range 8 .. 15; + nWRP at 0 range 16 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- FLASH + type FLASH_Peripheral is record + -- Flash access control register + ACR : aliased ACR_Register; + -- Flash key register + KEYR : aliased HAL.UInt32; + -- Flash option key register + OPTKEYR : aliased HAL.UInt32; + -- Status register + SR : aliased SR_Register; + -- Control register + CR : aliased CR_Register; + -- Flash option control register + OPTCR : aliased OPTCR_Register; + end record + with Volatile; + + for FLASH_Peripheral use record + ACR at 16#0# range 0 .. 31; + KEYR at 16#4# range 0 .. 31; + OPTKEYR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; + CR at 16#10# range 0 .. 31; + OPTCR at 16#14# range 0 .. 31; + end record; + + -- FLASH + FLASH_Periph : aliased FLASH_Peripheral + with Import, Address => FLASH_Base; + +end STM32_SVD.FLASH; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-fpu.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-fpu.ads new file mode 100644 index 000000000..0b2f9c067 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-fpu.ads @@ -0,0 +1,201 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.FPU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Floating-point context control register + type FPCCR_Register is record + -- LSPACT + LSPACT : Boolean := False; + -- USER + USER : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- THREAD + THREAD : Boolean := False; + -- HFRDY + HFRDY : Boolean := False; + -- MMRDY + MMRDY : Boolean := False; + -- BFRDY + BFRDY : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- MONRDY + MONRDY : Boolean := False; + -- unspecified + Reserved_9_29 : HAL.UInt21 := 16#0#; + -- LSPEN + LSPEN : Boolean := False; + -- ASPEN + ASPEN : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCCR_Register use record + LSPACT at 0 range 0 .. 0; + USER at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + THREAD at 0 range 3 .. 3; + HFRDY at 0 range 4 .. 4; + MMRDY at 0 range 5 .. 5; + BFRDY at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MONRDY at 0 range 8 .. 8; + Reserved_9_29 at 0 range 9 .. 29; + LSPEN at 0 range 30 .. 30; + ASPEN at 0 range 31 .. 31; + end record; + + subtype FPCAR_ADDRESS_Field is HAL.UInt29; + + -- Floating-point context address register + type FPCAR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Location of unpopulated floating-point + ADDRESS : FPCAR_ADDRESS_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCAR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + ADDRESS at 0 range 3 .. 31; + end record; + + subtype FPSCR_RMode_Field is HAL.UInt2; + + -- Floating-point status control register + type FPSCR_Register is record + -- Invalid operation cumulative exception bit + IOC : Boolean := False; + -- Division by zero cumulative exception bit. + DZC : Boolean := False; + -- Overflow cumulative exception bit + OFC : Boolean := False; + -- Underflow cumulative exception bit + UFC : Boolean := False; + -- Inexact cumulative exception bit + IXC : Boolean := False; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Input denormal cumulative exception bit. + IDC : Boolean := False; + -- unspecified + Reserved_8_21 : HAL.UInt14 := 16#0#; + -- Rounding Mode control field + RMode : FPSCR_RMode_Field := 16#0#; + -- Flush-to-zero mode control bit: + FZ : Boolean := False; + -- Default NaN mode control bit + DN : Boolean := False; + -- Alternative half-precision control bit + AHP : Boolean := False; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Overflow condition code flag + V : Boolean := False; + -- Carry condition code flag + C : Boolean := False; + -- Zero condition code flag + Z : Boolean := False; + -- Negative condition code flag + N : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPSCR_Register use record + IOC at 0 range 0 .. 0; + DZC at 0 range 1 .. 1; + OFC at 0 range 2 .. 2; + UFC at 0 range 3 .. 3; + IXC at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + IDC at 0 range 7 .. 7; + Reserved_8_21 at 0 range 8 .. 21; + RMode at 0 range 22 .. 23; + FZ at 0 range 24 .. 24; + DN at 0 range 25 .. 25; + AHP at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + V at 0 range 28 .. 28; + C at 0 range 29 .. 29; + Z at 0 range 30 .. 30; + N at 0 range 31 .. 31; + end record; + + subtype CPACR_CP_Field is HAL.UInt4; + + -- Coprocessor access control register + type CPACR_Register is record + -- unspecified + Reserved_0_19 : HAL.UInt20 := 16#0#; + -- CP + CP : CPACR_CP_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPACR_Register use record + Reserved_0_19 at 0 range 0 .. 19; + CP at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Floting point unit + type FPU_Peripheral is record + -- Floating-point context control register + FPCCR : aliased FPCCR_Register; + -- Floating-point context address register + FPCAR : aliased FPCAR_Register; + -- Floating-point status control register + FPSCR : aliased FPSCR_Register; + end record + with Volatile; + + for FPU_Peripheral use record + FPCCR at 16#0# range 0 .. 31; + FPCAR at 16#4# range 0 .. 31; + FPSCR at 16#8# range 0 .. 31; + end record; + + -- Floting point unit + FPU_Periph : aliased FPU_Peripheral + with Import, Address => FPU_Base; + + -- Floating point unit CPACR + type FPU_CPACR_Peripheral is record + -- Coprocessor access control register + CPACR : aliased CPACR_Register; + end record + with Volatile; + + for FPU_CPACR_Peripheral use record + CPACR at 0 range 0 .. 31; + end record; + + -- Floating point unit CPACR + FPU_CPACR_Periph : aliased FPU_CPACR_Peripheral + with Import, Address => FPU_CPACR_Base; + +end STM32_SVD.FPU; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-gpio.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-gpio.ads new file mode 100644 index 000000000..77446575f --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-gpio.ads @@ -0,0 +1,445 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.GPIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- MODER array element + subtype MODER_Element is HAL.UInt2; + + -- MODER array + type MODER_Field_Array is array (0 .. 15) of MODER_Element + with Component_Size => 2, Size => 32; + + -- GPIO port mode register + type MODER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- MODER as a value + Val : HAL.UInt32; + when True => + -- MODER as an array + Arr : MODER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- OTYPER_OT array + type OTYPER_OT_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for OTYPER_OT + type OTYPER_OT_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OT as a value + Val : HAL.UInt16; + when True => + -- OT as an array + Arr : OTYPER_OT_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for OTYPER_OT_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- GPIO port output type register + type OTYPER_Register is record + -- Port x configuration bits (y = 0..15) + OT : OTYPER_OT_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTYPER_Register use record + OT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- OSPEEDR array element + subtype OSPEEDR_Element is HAL.UInt2; + + -- OSPEEDR array + type OSPEEDR_Field_Array is array (0 .. 15) of OSPEEDR_Element + with Component_Size => 2, Size => 32; + + -- GPIO port output speed register + type OSPEEDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSPEEDR as a value + Val : HAL.UInt32; + when True => + -- OSPEEDR as an array + Arr : OSPEEDR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OSPEEDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PUPDR array element + subtype PUPDR_Element is HAL.UInt2; + + -- PUPDR array + type PUPDR_Field_Array is array (0 .. 15) of PUPDR_Element + with Component_Size => 2, Size => 32; + + -- GPIO port pull-up/pull-down register + type PUPDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PUPDR as a value + Val : HAL.UInt32; + when True => + -- PUPDR as an array + Arr : PUPDR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PUPDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IDR array + type IDR_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IDR + type IDR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IDR as a value + Val : HAL.UInt16; + when True => + -- IDR as an array + Arr : IDR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IDR_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- GPIO port input data register + type IDR_Register is record + -- Read-only. Port input data (y = 0..15) + IDR : IDR_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IDR_Register use record + IDR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- ODR array + type ODR_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for ODR + type ODR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ODR as a value + Val : HAL.UInt16; + when True => + -- ODR as an array + Arr : ODR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for ODR_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- GPIO port output data register + type ODR_Register is record + -- Port output data (y = 0..15) + ODR : ODR_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ODR_Register use record + ODR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- BSRR_BS array + type BSRR_BS_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for BSRR_BS + type BSRR_BS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- BS as a value + Val : HAL.UInt16; + when True => + -- BS as an array + Arr : BSRR_BS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for BSRR_BS_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- BSRR_BR array + type BSRR_BR_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for BSRR_BR + type BSRR_BR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- BR as a value + Val : HAL.UInt16; + when True => + -- BR as an array + Arr : BSRR_BR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for BSRR_BR_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- GPIO port bit set/reset register + type BSRR_Register is record + -- Write-only. Port x set bit y (y= 0..15) + BS : BSRR_BS_Field := (As_Array => False, Val => 16#0#); + -- Write-only. Port x set bit y (y= 0..15) + BR : BSRR_BR_Field := (As_Array => False, Val => 16#0#); + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BSRR_Register use record + BS at 0 range 0 .. 15; + BR at 0 range 16 .. 31; + end record; + + -- LCKR_LCK array + type LCKR_LCK_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for LCKR_LCK + type LCKR_LCK_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- LCK as a value + Val : HAL.UInt16; + when True => + -- LCK as an array + Arr : LCKR_LCK_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for LCKR_LCK_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- GPIO port configuration lock register + type LCKR_Register is record + -- Port x lock bit y (y= 0..15) + LCK : LCKR_LCK_Field := (As_Array => False, Val => 16#0#); + -- Port x lock bit y (y= 0..15) + LCKK : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LCKR_Register use record + LCK at 0 range 0 .. 15; + LCKK at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- AFRL array element + subtype AFRL_Element is HAL.UInt4; + + -- AFRL array + type AFRL_Field_Array is array (0 .. 7) of AFRL_Element + with Component_Size => 4, Size => 32; + + -- GPIO alternate function low register + type AFRL_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- AFRL as a value + Val : HAL.UInt32; + when True => + -- AFRL as an array + Arr : AFRL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AFRL_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- AFRH array element + subtype AFRH_Element is HAL.UInt4; + + -- AFRH array + type AFRH_Field_Array is array (8 .. 15) of AFRH_Element + with Component_Size => 4, Size => 32; + + -- GPIO alternate function high register + type AFRH_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- AFRH as a value + Val : HAL.UInt32; + when True => + -- AFRH as an array + Arr : AFRH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AFRH_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- General-purpose I/Os + type GPIO_Peripheral is record + -- GPIO port mode register + MODER : aliased MODER_Register; + -- GPIO port output type register + OTYPER : aliased OTYPER_Register; + -- GPIO port output speed register + OSPEEDR : aliased OSPEEDR_Register; + -- GPIO port pull-up/pull-down register + PUPDR : aliased PUPDR_Register; + -- GPIO port input data register + IDR : aliased IDR_Register; + -- GPIO port output data register + ODR : aliased ODR_Register; + -- GPIO port bit set/reset register + BSRR : aliased BSRR_Register; + -- GPIO port configuration lock register + LCKR : aliased LCKR_Register; + -- GPIO alternate function low register + AFRL : aliased AFRL_Register; + -- GPIO alternate function high register + AFRH : aliased AFRH_Register; + end record + with Volatile; + + for GPIO_Peripheral use record + MODER at 16#0# range 0 .. 31; + OTYPER at 16#4# range 0 .. 31; + OSPEEDR at 16#8# range 0 .. 31; + PUPDR at 16#C# range 0 .. 31; + IDR at 16#10# range 0 .. 31; + ODR at 16#14# range 0 .. 31; + BSRR at 16#18# range 0 .. 31; + LCKR at 16#1C# range 0 .. 31; + AFRL at 16#20# range 0 .. 31; + AFRH at 16#24# range 0 .. 31; + end record; + + -- General-purpose I/Os + GPIOA_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOA_Base; + + -- General-purpose I/Os + GPIOB_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOB_Base; + + -- General-purpose I/Os + GPIOC_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOC_Base; + + -- General-purpose I/Os + GPIOD_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOD_Base; + + -- General-purpose I/Os + GPIOE_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOE_Base; + + -- General-purpose I/Os + GPIOH_Periph : aliased GPIO_Peripheral + with Import, Address => GPIOH_Base; + +end STM32_SVD.GPIO; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-i2c.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-i2c.ads new file mode 100644 index 000000000..7a5cb146f --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-i2c.ads @@ -0,0 +1,374 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.I2C is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control register 1 + type CR1_Register is record + -- Peripheral enable + PE : Boolean := False; + -- SMBus mode + SMBUS : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- SMBus type + SMBTYPE : Boolean := False; + -- ARP enable + ENARP : Boolean := False; + -- PEC enable + ENPEC : Boolean := False; + -- General call enable + ENGC : Boolean := False; + -- Clock stretching disable (Slave mode) + NOSTRETCH : Boolean := False; + -- Start generation + START : Boolean := False; + -- Stop generation + STOP : Boolean := False; + -- Acknowledge enable + ACK : Boolean := False; + -- Acknowledge/PEC Position (for data reception) + POS : Boolean := False; + -- Packet error checking + PEC : Boolean := False; + -- SMBus alert + ALERT : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Software reset + SWRST : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register use record + PE at 0 range 0 .. 0; + SMBUS at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + SMBTYPE at 0 range 3 .. 3; + ENARP at 0 range 4 .. 4; + ENPEC at 0 range 5 .. 5; + ENGC at 0 range 6 .. 6; + NOSTRETCH at 0 range 7 .. 7; + START at 0 range 8 .. 8; + STOP at 0 range 9 .. 9; + ACK at 0 range 10 .. 10; + POS at 0 range 11 .. 11; + PEC at 0 range 12 .. 12; + ALERT at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + SWRST at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CR2_FREQ_Field is HAL.UInt6; + + -- Control register 2 + type CR2_Register is record + -- Peripheral clock frequency + FREQ : CR2_FREQ_Field := 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Error interrupt enable + ITERREN : Boolean := False; + -- Event interrupt enable + ITEVTEN : Boolean := False; + -- Buffer interrupt enable + ITBUFEN : Boolean := False; + -- DMA requests enable + DMAEN : Boolean := False; + -- DMA last transfer + LAST : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register use record + FREQ at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ITERREN at 0 range 8 .. 8; + ITEVTEN at 0 range 9 .. 9; + ITBUFEN at 0 range 10 .. 10; + DMAEN at 0 range 11 .. 11; + LAST at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype OAR1_ADD7_Field is HAL.UInt7; + subtype OAR1_ADD10_Field is HAL.UInt2; + + -- Own address register 1 + type OAR1_Register is record + -- Interface address + ADD0 : Boolean := False; + -- Interface address + ADD7 : OAR1_ADD7_Field := 16#0#; + -- Interface address + ADD10 : OAR1_ADD10_Field := 16#0#; + -- unspecified + Reserved_10_14 : HAL.UInt5 := 16#0#; + -- Addressing mode (slave mode) + ADDMODE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OAR1_Register use record + ADD0 at 0 range 0 .. 0; + ADD7 at 0 range 1 .. 7; + ADD10 at 0 range 8 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + ADDMODE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype OAR2_ADD2_Field is HAL.UInt7; + + -- Own address register 2 + type OAR2_Register is record + -- Dual addressing mode enable + ENDUAL : Boolean := False; + -- Interface address + ADD2 : OAR2_ADD2_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OAR2_Register use record + ENDUAL at 0 range 0 .. 0; + ADD2 at 0 range 1 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DR_DR_Field is HAL.UInt8; + + -- Data register + type DR_Register is record + -- 8-bit data register + DR : DR_DR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DR_Register use record + DR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Status register 1 + type SR1_Register is record + -- Read-only. Start bit (Master mode) + SB : Boolean := False; + -- Read-only. Address sent (master mode)/matched (slave mode) + ADDR : Boolean := False; + -- Read-only. Byte transfer finished + BTF : Boolean := False; + -- Read-only. 10-bit header sent (Master mode) + ADD10 : Boolean := False; + -- Read-only. Stop detection (slave mode) + STOPF : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Read-only. Data register not empty (receivers) + RxNE : Boolean := False; + -- Read-only. Data register empty (transmitters) + TxE : Boolean := False; + -- Bus error + BERR : Boolean := False; + -- Arbitration lost (master mode) + ARLO : Boolean := False; + -- Acknowledge failure + AF : Boolean := False; + -- Overrun/Underrun + OVR : Boolean := False; + -- PEC Error in reception + PECERR : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Timeout or Tlow error + TIMEOUT : Boolean := False; + -- SMBus alert + SMBALERT : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR1_Register use record + SB at 0 range 0 .. 0; + ADDR at 0 range 1 .. 1; + BTF at 0 range 2 .. 2; + ADD10 at 0 range 3 .. 3; + STOPF at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + RxNE at 0 range 6 .. 6; + TxE at 0 range 7 .. 7; + BERR at 0 range 8 .. 8; + ARLO at 0 range 9 .. 9; + AF at 0 range 10 .. 10; + OVR at 0 range 11 .. 11; + PECERR at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + TIMEOUT at 0 range 14 .. 14; + SMBALERT at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SR2_PEC_Field is HAL.UInt8; + + -- Status register 2 + type SR2_Register is record + -- Read-only. Master/slave + MSL : Boolean; + -- Read-only. Bus busy + BUSY : Boolean; + -- Read-only. Transmitter/receiver + TRA : Boolean; + -- unspecified + Reserved_3_3 : HAL.Bit; + -- Read-only. General call address (Slave mode) + GENCALL : Boolean; + -- Read-only. SMBus device default address (Slave mode) + SMBDEFAULT : Boolean; + -- Read-only. SMBus host header (Slave mode) + SMBHOST : Boolean; + -- Read-only. Dual flag (Slave mode) + DUALF : Boolean; + -- Read-only. acket error checking register + PEC : SR2_PEC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR2_Register use record + MSL at 0 range 0 .. 0; + BUSY at 0 range 1 .. 1; + TRA at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + GENCALL at 0 range 4 .. 4; + SMBDEFAULT at 0 range 5 .. 5; + SMBHOST at 0 range 6 .. 6; + DUALF at 0 range 7 .. 7; + PEC at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR_CCR_Field is HAL.UInt12; + + -- Clock control register + type CCR_Register is record + -- Clock control register in Fast/Standard mode (Master mode) + CCR : CCR_CCR_Field := 16#0#; + -- unspecified + Reserved_12_13 : HAL.UInt2 := 16#0#; + -- Fast mode duty cycle + DUTY : Boolean := False; + -- I2C master mode selection + F_S : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR_Register use record + CCR at 0 range 0 .. 11; + Reserved_12_13 at 0 range 12 .. 13; + DUTY at 0 range 14 .. 14; + F_S at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TRISE_TRISE_Field is HAL.UInt6; + + -- TRISE register + type TRISE_Register is record + -- Maximum rise time in Fast/Standard mode (Master mode) + TRISE : TRISE_TRISE_Field := 16#2#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRISE_Register use record + TRISE at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Inter-integrated circuit + type I2C_Peripheral is record + -- Control register 1 + CR1 : aliased CR1_Register; + -- Control register 2 + CR2 : aliased CR2_Register; + -- Own address register 1 + OAR1 : aliased OAR1_Register; + -- Own address register 2 + OAR2 : aliased OAR2_Register; + -- Data register + DR : aliased DR_Register; + -- Status register 1 + SR1 : aliased SR1_Register; + -- Status register 2 + SR2 : aliased SR2_Register; + -- Clock control register + CCR : aliased CCR_Register; + -- TRISE register + TRISE : aliased TRISE_Register; + end record + with Volatile; + + for I2C_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + OAR1 at 16#8# range 0 .. 31; + OAR2 at 16#C# range 0 .. 31; + DR at 16#10# range 0 .. 31; + SR1 at 16#14# range 0 .. 31; + SR2 at 16#18# range 0 .. 31; + CCR at 16#1C# range 0 .. 31; + TRISE at 16#20# range 0 .. 31; + end record; + + -- Inter-integrated circuit + I2C1_Periph : aliased I2C_Peripheral + with Import, Address => I2C1_Base; + + -- Inter-integrated circuit + I2C2_Periph : aliased I2C_Peripheral + with Import, Address => I2C2_Base; + + -- Inter-integrated circuit + I2C3_Periph : aliased I2C_Peripheral + with Import, Address => I2C3_Base; + +end STM32_SVD.I2C; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-iwdg.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-iwdg.ads new file mode 100644 index 000000000..a19fcb581 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-iwdg.ads @@ -0,0 +1,114 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.IWDG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype KR_KEY_Field is HAL.UInt16; + + -- Key register + type KR_Register is record + -- Write-only. Key value + KEY : KR_KEY_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KR_Register use record + KEY at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype PR_PR_Field is HAL.UInt3; + + -- Prescaler register + type PR_Register is record + -- Prescaler divider + PR : PR_PR_Field := 16#0#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PR_Register use record + PR at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype RLR_RL_Field is HAL.UInt12; + + -- Reload register + type RLR_Register is record + -- Watchdog counter reload value + RL : RLR_RL_Field := 16#FFF#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RLR_Register use record + RL at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Status register + type SR_Register is record + -- Read-only. Watchdog prescaler value update + PVU : Boolean; + -- Read-only. Watchdog counter reload value update + RVU : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + PVU at 0 range 0 .. 0; + RVU at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Independent watchdog + type IWDG_Peripheral is record + -- Key register + KR : aliased KR_Register; + -- Prescaler register + PR : aliased PR_Register; + -- Reload register + RLR : aliased RLR_Register; + -- Status register + SR : aliased SR_Register; + end record + with Volatile; + + for IWDG_Peripheral use record + KR at 16#0# range 0 .. 31; + PR at 16#4# range 0 .. 31; + RLR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; + end record; + + -- Independent watchdog + IWDG_Periph : aliased IWDG_Peripheral + with Import, Address => IWDG_Base; + +end STM32_SVD.IWDG; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-mpu.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-mpu.ads new file mode 100644 index 000000000..57f65f84a --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-mpu.ads @@ -0,0 +1,187 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.MPU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype MPU_TYPER_DREGION_Field is HAL.UInt8; + subtype MPU_TYPER_IREGION_Field is HAL.UInt8; + + -- MPU type register + type MPU_TYPER_Register is record + -- Read-only. Separate flag + SEPARATE_k : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Number of MPU data regions + DREGION : MPU_TYPER_DREGION_Field; + -- Read-only. Number of MPU instruction regions + IREGION : MPU_TYPER_IREGION_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_TYPER_Register use record + SEPARATE_k at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + DREGION at 0 range 8 .. 15; + IREGION at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- MPU control register + type MPU_CTRL_Register is record + -- Read-only. Enables the MPU + ENABLE : Boolean; + -- Read-only. Enables the operation of MPU during hard fault + HFNMIENA : Boolean; + -- Read-only. Enable priviliged software access to default memory map + PRIVDEFENA : Boolean; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + HFNMIENA at 0 range 1 .. 1; + PRIVDEFENA at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_RNR_REGION_Field is HAL.UInt8; + + -- MPU region number register + type MPU_RNR_Register is record + -- MPU region + REGION : MPU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RNR_Register use record + REGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype MPU_RBAR_REGION_Field is HAL.UInt4; + subtype MPU_RBAR_ADDR_Field is HAL.UInt27; + + -- MPU region base address register + type MPU_RBAR_Register is record + -- MPU region field + REGION : MPU_RBAR_REGION_Field := 16#0#; + -- MPU region number valid + VALID : Boolean := False; + -- Region base address field + ADDR : MPU_RBAR_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RBAR_Register use record + REGION at 0 range 0 .. 3; + VALID at 0 range 4 .. 4; + ADDR at 0 range 5 .. 31; + end record; + + subtype MPU_RASR_SIZE_Field is HAL.UInt5; + subtype MPU_RASR_SRD_Field is HAL.UInt8; + subtype MPU_RASR_TEX_Field is HAL.UInt3; + subtype MPU_RASR_AP_Field is HAL.UInt3; + + -- MPU region attribute and size register + type MPU_RASR_Register is record + -- Region enable bit. + ENABLE : Boolean := False; + -- Size of the MPU protection region + SIZE : MPU_RASR_SIZE_Field := 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Subregion disable bits + SRD : MPU_RASR_SRD_Field := 16#0#; + -- memory attribute + B : Boolean := False; + -- memory attribute + C : Boolean := False; + -- Shareable memory attribute + S : Boolean := False; + -- memory attribute + TEX : MPU_RASR_TEX_Field := 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Access permission + AP : MPU_RASR_AP_Field := 16#0#; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Instruction access disable bit + XN : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RASR_Register use record + ENABLE at 0 range 0 .. 0; + SIZE at 0 range 1 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SRD at 0 range 8 .. 15; + B at 0 range 16 .. 16; + C at 0 range 17 .. 17; + S at 0 range 18 .. 18; + TEX at 0 range 19 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + AP at 0 range 24 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + XN at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Memory protection unit + type MPU_Peripheral is record + -- MPU type register + MPU_TYPER : aliased MPU_TYPER_Register; + -- MPU control register + MPU_CTRL : aliased MPU_CTRL_Register; + -- MPU region number register + MPU_RNR : aliased MPU_RNR_Register; + -- MPU region base address register + MPU_RBAR : aliased MPU_RBAR_Register; + -- MPU region attribute and size register + MPU_RASR : aliased MPU_RASR_Register; + end record + with Volatile; + + for MPU_Peripheral use record + MPU_TYPER at 16#0# range 0 .. 31; + MPU_CTRL at 16#4# range 0 .. 31; + MPU_RNR at 16#8# range 0 .. 31; + MPU_RBAR at 16#C# range 0 .. 31; + MPU_RASR at 16#10# range 0 .. 31; + end record; + + -- Memory protection unit + MPU_Periph : aliased MPU_Peripheral + with Import, Address => MPU_Base; + +end STM32_SVD.MPU; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-nvic.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-nvic.ads new file mode 100644 index 000000000..2a6af54a5 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-nvic.ads @@ -0,0 +1,198 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.NVIC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- IPR_IPR_N array element + subtype IPR_IPR_N_Element is HAL.UInt8; + + -- IPR_IPR_N array + type IPR_IPR_N_Field_Array is array (0 .. 3) of IPR_IPR_N_Element + with Component_Size => 8, Size => 32; + + -- Interrupt Priority Register + type IPR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IPR_N as a value + Val : HAL.UInt32; + when True => + -- IPR_N as an array + Arr : IPR_IPR_N_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IPR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype STIR_INTID_Field is HAL.UInt9; + + -- Software trigger interrupt register + type STIR_Register is record + -- Software generated interrupt ID + INTID : STIR_INTID_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STIR_Register use record + INTID at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Nested Vectored Interrupt Controller + type NVIC_Peripheral is record + -- Interrupt Set-Enable Register + ISER0 : aliased HAL.UInt32; + -- Interrupt Set-Enable Register + ISER1 : aliased HAL.UInt32; + -- Interrupt Set-Enable Register + ISER2 : aliased HAL.UInt32; + -- Interrupt Clear-Enable Register + ICER0 : aliased HAL.UInt32; + -- Interrupt Clear-Enable Register + ICER1 : aliased HAL.UInt32; + -- Interrupt Clear-Enable Register + ICER2 : aliased HAL.UInt32; + -- Interrupt Set-Pending Register + ISPR0 : aliased HAL.UInt32; + -- Interrupt Set-Pending Register + ISPR1 : aliased HAL.UInt32; + -- Interrupt Set-Pending Register + ISPR2 : aliased HAL.UInt32; + -- Interrupt Clear-Pending Register + ICPR0 : aliased HAL.UInt32; + -- Interrupt Clear-Pending Register + ICPR1 : aliased HAL.UInt32; + -- Interrupt Clear-Pending Register + ICPR2 : aliased HAL.UInt32; + -- Interrupt Active Bit Register + IABR0 : aliased HAL.UInt32; + -- Interrupt Active Bit Register + IABR1 : aliased HAL.UInt32; + -- Interrupt Active Bit Register + IABR2 : aliased HAL.UInt32; + -- Interrupt Priority Register + IPR0 : aliased IPR_Register; + -- Interrupt Priority Register + IPR1 : aliased IPR_Register; + -- Interrupt Priority Register + IPR2 : aliased IPR_Register; + -- Interrupt Priority Register + IPR3 : aliased IPR_Register; + -- Interrupt Priority Register + IPR4 : aliased IPR_Register; + -- Interrupt Priority Register + IPR5 : aliased IPR_Register; + -- Interrupt Priority Register + IPR6 : aliased IPR_Register; + -- Interrupt Priority Register + IPR7 : aliased IPR_Register; + -- Interrupt Priority Register + IPR8 : aliased IPR_Register; + -- Interrupt Priority Register + IPR9 : aliased IPR_Register; + -- Interrupt Priority Register + IPR10 : aliased IPR_Register; + -- Interrupt Priority Register + IPR11 : aliased IPR_Register; + -- Interrupt Priority Register + IPR12 : aliased IPR_Register; + -- Interrupt Priority Register + IPR13 : aliased IPR_Register; + -- Interrupt Priority Register + IPR14 : aliased IPR_Register; + -- Interrupt Priority Register + IPR15 : aliased IPR_Register; + -- Interrupt Priority Register + IPR16 : aliased IPR_Register; + -- Interrupt Priority Register + IPR17 : aliased IPR_Register; + -- Interrupt Priority Register + IPR18 : aliased IPR_Register; + -- Interrupt Priority Register + IPR19 : aliased IPR_Register; + end record + with Volatile; + + for NVIC_Peripheral use record + ISER0 at 16#0# range 0 .. 31; + ISER1 at 16#4# range 0 .. 31; + ISER2 at 16#8# range 0 .. 31; + ICER0 at 16#80# range 0 .. 31; + ICER1 at 16#84# range 0 .. 31; + ICER2 at 16#88# range 0 .. 31; + ISPR0 at 16#100# range 0 .. 31; + ISPR1 at 16#104# range 0 .. 31; + ISPR2 at 16#108# range 0 .. 31; + ICPR0 at 16#180# range 0 .. 31; + ICPR1 at 16#184# range 0 .. 31; + ICPR2 at 16#188# range 0 .. 31; + IABR0 at 16#200# range 0 .. 31; + IABR1 at 16#204# range 0 .. 31; + IABR2 at 16#208# range 0 .. 31; + IPR0 at 16#300# range 0 .. 31; + IPR1 at 16#304# range 0 .. 31; + IPR2 at 16#308# range 0 .. 31; + IPR3 at 16#30C# range 0 .. 31; + IPR4 at 16#310# range 0 .. 31; + IPR5 at 16#314# range 0 .. 31; + IPR6 at 16#318# range 0 .. 31; + IPR7 at 16#31C# range 0 .. 31; + IPR8 at 16#320# range 0 .. 31; + IPR9 at 16#324# range 0 .. 31; + IPR10 at 16#328# range 0 .. 31; + IPR11 at 16#32C# range 0 .. 31; + IPR12 at 16#330# range 0 .. 31; + IPR13 at 16#334# range 0 .. 31; + IPR14 at 16#338# range 0 .. 31; + IPR15 at 16#33C# range 0 .. 31; + IPR16 at 16#340# range 0 .. 31; + IPR17 at 16#344# range 0 .. 31; + IPR18 at 16#348# range 0 .. 31; + IPR19 at 16#34C# range 0 .. 31; + end record; + + -- Nested Vectored Interrupt Controller + NVIC_Periph : aliased NVIC_Peripheral + with Import, Address => NVIC_Base; + + -- Nested vectored interrupt controller + type NVIC_STIR_Peripheral is record + -- Software trigger interrupt register + STIR : aliased STIR_Register; + end record + with Volatile; + + for NVIC_STIR_Peripheral use record + STIR at 0 range 0 .. 31; + end record; + + -- Nested vectored interrupt controller + NVIC_STIR_Periph : aliased NVIC_STIR_Peripheral + with Import, Address => NVIC_STIR_Base; + +end STM32_SVD.NVIC; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-pwr.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-pwr.ads new file mode 100644 index 000000000..85ae0d9b4 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-pwr.ads @@ -0,0 +1,126 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.PWR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CR_PLS_Field is HAL.UInt3; + subtype CR_VOS_Field is HAL.UInt2; + + -- power control register + type CR_Register is record + -- Low-power deep sleep + LPDS : Boolean := False; + -- Power down deepsleep + PDDS : Boolean := False; + -- Clear wakeup flag + CWUF : Boolean := False; + -- Clear standby flag + CSBF : Boolean := False; + -- Power voltage detector enable + PVDE : Boolean := False; + -- PVD level selection + PLS : CR_PLS_Field := 16#0#; + -- Disable backup domain write protection + DBP : Boolean := False; + -- Flash power down in Stop mode + FPDS : Boolean := False; + -- unspecified + Reserved_10_12 : HAL.UInt3 := 16#0#; + -- ADCDC1 + ADCDC1 : Boolean := False; + -- Regulator voltage scaling output selection + VOS : CR_VOS_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + LPDS at 0 range 0 .. 0; + PDDS at 0 range 1 .. 1; + CWUF at 0 range 2 .. 2; + CSBF at 0 range 3 .. 3; + PVDE at 0 range 4 .. 4; + PLS at 0 range 5 .. 7; + DBP at 0 range 8 .. 8; + FPDS at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + ADCDC1 at 0 range 13 .. 13; + VOS at 0 range 14 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- power control/status register + type CSR_Register is record + -- Read-only. Wakeup flag + WUF : Boolean := False; + -- Read-only. Standby flag + SBF : Boolean := False; + -- Read-only. PVD output + PVDO : Boolean := False; + -- Read-only. Backup regulator ready + BRR : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Enable WKUP pin + EWUP : Boolean := False; + -- Backup regulator enable + BRE : Boolean := False; + -- unspecified + Reserved_10_13 : HAL.UInt4 := 16#0#; + -- Regulator voltage scaling output selection ready bit + VOSRDY : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSR_Register use record + WUF at 0 range 0 .. 0; + SBF at 0 range 1 .. 1; + PVDO at 0 range 2 .. 2; + BRR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + EWUP at 0 range 8 .. 8; + BRE at 0 range 9 .. 9; + Reserved_10_13 at 0 range 10 .. 13; + VOSRDY at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Power control + type PWR_Peripheral is record + -- power control register + CR : aliased CR_Register; + -- power control/status register + CSR : aliased CSR_Register; + end record + with Volatile; + + for PWR_Peripheral use record + CR at 16#0# range 0 .. 31; + CSR at 16#4# range 0 .. 31; + end record; + + -- Power control + PWR_Periph : aliased PWR_Peripheral + with Import, Address => PWR_Base; + +end STM32_SVD.PWR; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-rcc.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-rcc.ads new file mode 100644 index 000000000..88eff78b3 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-rcc.ads @@ -0,0 +1,1075 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.RCC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CR_HSITRIM_Field is HAL.UInt5; + subtype CR_HSICAL_Field is HAL.UInt8; + + -- clock control register + type CR_Register is record + -- Internal high-speed clock enable + HSION : Boolean := True; + -- Read-only. Internal high-speed clock ready flag + HSIRDY : Boolean := True; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Internal high-speed clock trimming + HSITRIM : CR_HSITRIM_Field := 16#10#; + -- Read-only. Internal high-speed clock calibration + HSICAL : CR_HSICAL_Field := 16#0#; + -- HSE clock enable + HSEON : Boolean := False; + -- Read-only. HSE clock ready flag + HSERDY : Boolean := False; + -- HSE clock bypass + HSEBYP : Boolean := False; + -- Clock security system enable + CSSON : Boolean := False; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Main PLL (PLL) enable + PLLON : Boolean := False; + -- Read-only. Main PLL (PLL) clock ready flag + PLLRDY : Boolean := False; + -- PLLI2S enable + PLLI2SON : Boolean := False; + -- Read-only. PLLI2S clock ready flag + PLLI2SRDY : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + HSION at 0 range 0 .. 0; + HSIRDY at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + HSITRIM at 0 range 3 .. 7; + HSICAL at 0 range 8 .. 15; + HSEON at 0 range 16 .. 16; + HSERDY at 0 range 17 .. 17; + HSEBYP at 0 range 18 .. 18; + CSSON at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + PLLON at 0 range 24 .. 24; + PLLRDY at 0 range 25 .. 25; + PLLI2SON at 0 range 26 .. 26; + PLLI2SRDY at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype PLLCFGR_PLLM_Field is HAL.UInt6; + subtype PLLCFGR_PLLN_Field is HAL.UInt9; + subtype PLLCFGR_PLLP_Field is HAL.UInt2; + subtype PLLCFGR_PLLQ_Field is HAL.UInt4; + + -- PLL configuration register + type PLLCFGR_Register is record + -- Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input + -- clock + PLLM : PLLCFGR_PLLM_Field := 16#10#; + -- Main PLL (PLL) multiplication factor for VCO + PLLN : PLLCFGR_PLLN_Field := 16#C0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Main PLL (PLL) division factor for main system clock + PLLP : PLLCFGR_PLLP_Field := 16#0#; + -- unspecified + Reserved_18_21 : HAL.UInt4 := 16#0#; + -- Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC : Boolean := False; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Main PLL (PLL) division factor for USB OTG FS, SDIO and random number + -- generator clocks + PLLQ : PLLCFGR_PLLQ_Field := 16#4#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#2#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLLCFGR_Register use record + PLLM at 0 range 0 .. 5; + PLLN at 0 range 6 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PLLP at 0 range 16 .. 17; + Reserved_18_21 at 0 range 18 .. 21; + PLLSRC at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + PLLQ at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype CFGR_SW_Field is HAL.UInt2; + subtype CFGR_SWS_Field is HAL.UInt2; + subtype CFGR_HPRE_Field is HAL.UInt4; + -- CFGR_PPRE array element + subtype CFGR_PPRE_Element is HAL.UInt3; + + -- CFGR_PPRE array + type CFGR_PPRE_Field_Array is array (1 .. 2) of CFGR_PPRE_Element + with Component_Size => 3, Size => 6; + + -- Type definition for CFGR_PPRE + type CFGR_PPRE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PPRE as a value + Val : HAL.UInt6; + when True => + -- PPRE as an array + Arr : CFGR_PPRE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for CFGR_PPRE_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + subtype CFGR_RTCPRE_Field is HAL.UInt5; + subtype CFGR_MCO1_Field is HAL.UInt2; + subtype CFGR_MCO1PRE_Field is HAL.UInt3; + subtype CFGR_MCO2PRE_Field is HAL.UInt3; + subtype CFGR_MCO2_Field is HAL.UInt2; + + -- clock configuration register + type CFGR_Register is record + -- System clock switch + SW : CFGR_SW_Field := 16#0#; + -- Read-only. System clock switch status + SWS : CFGR_SWS_Field := 16#0#; + -- AHB prescaler + HPRE : CFGR_HPRE_Field := 16#0#; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- APB Low speed prescaler (APB1) + PPRE : CFGR_PPRE_Field := (As_Array => False, Val => 16#0#); + -- HSE division factor for RTC clock + RTCPRE : CFGR_RTCPRE_Field := 16#0#; + -- Microcontroller clock output 1 + MCO1 : CFGR_MCO1_Field := 16#0#; + -- I2S clock selection + I2SSRC : Boolean := False; + -- MCO1 prescaler + MCO1PRE : CFGR_MCO1PRE_Field := 16#0#; + -- MCO2 prescaler + MCO2PRE : CFGR_MCO2PRE_Field := 16#0#; + -- Microcontroller clock output 2 + MCO2 : CFGR_MCO2_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFGR_Register use record + SW at 0 range 0 .. 1; + SWS at 0 range 2 .. 3; + HPRE at 0 range 4 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + PPRE at 0 range 10 .. 15; + RTCPRE at 0 range 16 .. 20; + MCO1 at 0 range 21 .. 22; + I2SSRC at 0 range 23 .. 23; + MCO1PRE at 0 range 24 .. 26; + MCO2PRE at 0 range 27 .. 29; + MCO2 at 0 range 30 .. 31; + end record; + + -- clock interrupt register + type CIR_Register is record + -- Read-only. LSI ready interrupt flag + LSIRDYF : Boolean := False; + -- Read-only. LSE ready interrupt flag + LSERDYF : Boolean := False; + -- Read-only. HSI ready interrupt flag + HSIRDYF : Boolean := False; + -- Read-only. HSE ready interrupt flag + HSERDYF : Boolean := False; + -- Read-only. Main PLL (PLL) ready interrupt flag + PLLRDYF : Boolean := False; + -- Read-only. PLLI2S ready interrupt flag + PLLI2SRDYF : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Read-only. Clock security system interrupt flag + CSSF : Boolean := False; + -- LSI ready interrupt enable + LSIRDYIE : Boolean := False; + -- LSE ready interrupt enable + LSERDYIE : Boolean := False; + -- HSI ready interrupt enable + HSIRDYIE : Boolean := False; + -- HSE ready interrupt enable + HSERDYIE : Boolean := False; + -- Main PLL (PLL) ready interrupt enable + PLLRDYIE : Boolean := False; + -- PLLI2S ready interrupt enable + PLLI2SRDYIE : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Write-only. LSI ready interrupt clear + LSIRDYC : Boolean := False; + -- Write-only. LSE ready interrupt clear + LSERDYC : Boolean := False; + -- Write-only. HSI ready interrupt clear + HSIRDYC : Boolean := False; + -- Write-only. HSE ready interrupt clear + HSERDYC : Boolean := False; + -- Write-only. Main PLL(PLL) ready interrupt clear + PLLRDYC : Boolean := False; + -- Write-only. PLLI2S ready interrupt clear + PLLI2SRDYC : Boolean := False; + -- unspecified + Reserved_22_22 : HAL.Bit := 16#0#; + -- Write-only. Clock security system interrupt clear + CSSC : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIR_Register use record + LSIRDYF at 0 range 0 .. 0; + LSERDYF at 0 range 1 .. 1; + HSIRDYF at 0 range 2 .. 2; + HSERDYF at 0 range 3 .. 3; + PLLRDYF at 0 range 4 .. 4; + PLLI2SRDYF at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + CSSF at 0 range 7 .. 7; + LSIRDYIE at 0 range 8 .. 8; + LSERDYIE at 0 range 9 .. 9; + HSIRDYIE at 0 range 10 .. 10; + HSERDYIE at 0 range 11 .. 11; + PLLRDYIE at 0 range 12 .. 12; + PLLI2SRDYIE at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + LSIRDYC at 0 range 16 .. 16; + LSERDYC at 0 range 17 .. 17; + HSIRDYC at 0 range 18 .. 18; + HSERDYC at 0 range 19 .. 19; + PLLRDYC at 0 range 20 .. 20; + PLLI2SRDYC at 0 range 21 .. 21; + Reserved_22_22 at 0 range 22 .. 22; + CSSC at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- AHB1 peripheral reset register + type AHB1RSTR_Register is record + -- IO port A reset + GPIOARST : Boolean := False; + -- IO port B reset + GPIOBRST : Boolean := False; + -- IO port C reset + GPIOCRST : Boolean := False; + -- IO port D reset + GPIODRST : Boolean := False; + -- IO port E reset + GPIOERST : Boolean := False; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- IO port H reset + GPIOHRST : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- CRC reset + CRCRST : Boolean := False; + -- unspecified + Reserved_13_20 : HAL.UInt8 := 16#0#; + -- DMA2 reset + DMA1RST : Boolean := False; + -- DMA2 reset + DMA2RST : Boolean := False; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB1RSTR_Register use record + GPIOARST at 0 range 0 .. 0; + GPIOBRST at 0 range 1 .. 1; + GPIOCRST at 0 range 2 .. 2; + GPIODRST at 0 range 3 .. 3; + GPIOERST at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + GPIOHRST at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + CRCRST at 0 range 12 .. 12; + Reserved_13_20 at 0 range 13 .. 20; + DMA1RST at 0 range 21 .. 21; + DMA2RST at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- AHB2 peripheral reset register + type AHB2RSTR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- USB OTG FS module reset + OTGFSRST : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB2RSTR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + OTGFSRST at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- APB1 peripheral reset register + type APB1RSTR_Register is record + -- TIM2 reset + TIM2RST : Boolean := False; + -- TIM3 reset + TIM3RST : Boolean := False; + -- TIM4 reset + TIM4RST : Boolean := False; + -- TIM5 reset + TIM5RST : Boolean := False; + -- unspecified + Reserved_4_10 : HAL.UInt7 := 16#0#; + -- Window watchdog reset + WWDGRST : Boolean := False; + -- unspecified + Reserved_12_13 : HAL.UInt2 := 16#0#; + -- SPI 2 reset + SPI2RST : Boolean := False; + -- SPI 3 reset + SPI3RST : Boolean := False; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- USART 2 reset + UART2RST : Boolean := False; + -- unspecified + Reserved_18_20 : HAL.UInt3 := 16#0#; + -- I2C 1 reset + I2C1RST : Boolean := False; + -- I2C 2 reset + I2C2RST : Boolean := False; + -- I2C3 reset + I2C3RST : Boolean := False; + -- unspecified + Reserved_24_27 : HAL.UInt4 := 16#0#; + -- Power interface reset + PWRRST : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB1RSTR_Register use record + TIM2RST at 0 range 0 .. 0; + TIM3RST at 0 range 1 .. 1; + TIM4RST at 0 range 2 .. 2; + TIM5RST at 0 range 3 .. 3; + Reserved_4_10 at 0 range 4 .. 10; + WWDGRST at 0 range 11 .. 11; + Reserved_12_13 at 0 range 12 .. 13; + SPI2RST at 0 range 14 .. 14; + SPI3RST at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + UART2RST at 0 range 17 .. 17; + Reserved_18_20 at 0 range 18 .. 20; + I2C1RST at 0 range 21 .. 21; + I2C2RST at 0 range 22 .. 22; + I2C3RST at 0 range 23 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + PWRRST at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- APB2 peripheral reset register + type APB2RSTR_Register is record + -- TIM1 reset + TIM1RST : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- USART1 reset + USART1RST : Boolean := False; + -- USART6 reset + USART6RST : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- ADC interface reset (common to all ADCs) + ADCRST : Boolean := False; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- SDIO reset + SDIORST : Boolean := False; + -- SPI 1 reset + SPI1RST : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- System configuration controller reset + SYSCFGRST : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- TIM9 reset + TIM9RST : Boolean := False; + -- TIM10 reset + TIM10RST : Boolean := False; + -- TIM11 reset + TIM11RST : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB2RSTR_Register use record + TIM1RST at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + USART1RST at 0 range 4 .. 4; + USART6RST at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ADCRST at 0 range 8 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + SDIORST at 0 range 11 .. 11; + SPI1RST at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SYSCFGRST at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + TIM9RST at 0 range 16 .. 16; + TIM10RST at 0 range 17 .. 17; + TIM11RST at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- AHB1 peripheral clock register + type AHB1ENR_Register is record + -- IO port A clock enable + GPIOAEN : Boolean := False; + -- IO port B clock enable + GPIOBEN : Boolean := False; + -- IO port C clock enable + GPIOCEN : Boolean := False; + -- IO port D clock enable + GPIODEN : Boolean := False; + -- IO port E clock enable + GPIOEEN : Boolean := False; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- IO port H clock enable + GPIOHEN : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- CRC clock enable + CRCEN : Boolean := False; + -- unspecified + Reserved_13_20 : HAL.UInt8 := 16#80#; + -- DMA1 clock enable + DMA1EN : Boolean := False; + -- DMA2 clock enable + DMA2EN : Boolean := False; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB1ENR_Register use record + GPIOAEN at 0 range 0 .. 0; + GPIOBEN at 0 range 1 .. 1; + GPIOCEN at 0 range 2 .. 2; + GPIODEN at 0 range 3 .. 3; + GPIOEEN at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + GPIOHEN at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + CRCEN at 0 range 12 .. 12; + Reserved_13_20 at 0 range 13 .. 20; + DMA1EN at 0 range 21 .. 21; + DMA2EN at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- AHB2 peripheral clock enable register + type AHB2ENR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- USB OTG FS clock enable + OTGFSEN : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB2ENR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + OTGFSEN at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- APB1 peripheral clock enable register + type APB1ENR_Register is record + -- TIM2 clock enable + TIM2EN : Boolean := False; + -- TIM3 clock enable + TIM3EN : Boolean := False; + -- TIM4 clock enable + TIM4EN : Boolean := False; + -- TIM5 clock enable + TIM5EN : Boolean := False; + -- unspecified + Reserved_4_10 : HAL.UInt7 := 16#0#; + -- Window watchdog clock enable + WWDGEN : Boolean := False; + -- unspecified + Reserved_12_13 : HAL.UInt2 := 16#0#; + -- SPI2 clock enable + SPI2EN : Boolean := False; + -- SPI3 clock enable + SPI3EN : Boolean := False; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- USART 2 clock enable + USART2EN : Boolean := False; + -- unspecified + Reserved_18_20 : HAL.UInt3 := 16#0#; + -- I2C1 clock enable + I2C1EN : Boolean := False; + -- I2C2 clock enable + I2C2EN : Boolean := False; + -- I2C3 clock enable + I2C3EN : Boolean := False; + -- unspecified + Reserved_24_27 : HAL.UInt4 := 16#0#; + -- Power interface clock enable + PWREN : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB1ENR_Register use record + TIM2EN at 0 range 0 .. 0; + TIM3EN at 0 range 1 .. 1; + TIM4EN at 0 range 2 .. 2; + TIM5EN at 0 range 3 .. 3; + Reserved_4_10 at 0 range 4 .. 10; + WWDGEN at 0 range 11 .. 11; + Reserved_12_13 at 0 range 12 .. 13; + SPI2EN at 0 range 14 .. 14; + SPI3EN at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + USART2EN at 0 range 17 .. 17; + Reserved_18_20 at 0 range 18 .. 20; + I2C1EN at 0 range 21 .. 21; + I2C2EN at 0 range 22 .. 22; + I2C3EN at 0 range 23 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + PWREN at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- APB2 peripheral clock enable register + type APB2ENR_Register is record + -- TIM1 clock enable + TIM1EN : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- USART1 clock enable + USART1EN : Boolean := False; + -- USART6 clock enable + USART6EN : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- ADC1 clock enable + ADC1EN : Boolean := False; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- SDIO clock enable + SDIOEN : Boolean := False; + -- SPI1 clock enable + SPI1EN : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- System configuration controller clock enable + SYSCFGEN : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- TIM9 clock enable + TIM9EN : Boolean := False; + -- TIM10 clock enable + TIM10EN : Boolean := False; + -- TIM11 clock enable + TIM11EN : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB2ENR_Register use record + TIM1EN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + USART1EN at 0 range 4 .. 4; + USART6EN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ADC1EN at 0 range 8 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + SDIOEN at 0 range 11 .. 11; + SPI1EN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SYSCFGEN at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + TIM9EN at 0 range 16 .. 16; + TIM10EN at 0 range 17 .. 17; + TIM11EN at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- AHB1 peripheral clock enable in low power mode register + type AHB1LPENR_Register is record + -- IO port A clock enable during sleep mode + GPIOALPEN : Boolean := True; + -- IO port B clock enable during Sleep mode + GPIOBLPEN : Boolean := True; + -- IO port C clock enable during Sleep mode + GPIOCLPEN : Boolean := True; + -- IO port D clock enable during Sleep mode + GPIODLPEN : Boolean := True; + -- IO port E clock enable during Sleep mode + GPIOELPEN : Boolean := True; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#3#; + -- IO port H clock enable during Sleep mode + GPIOHLPEN : Boolean := True; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#1#; + -- CRC clock enable during Sleep mode + CRCLPEN : Boolean := True; + -- unspecified + Reserved_13_14 : HAL.UInt2 := 16#0#; + -- Flash interface clock enable during Sleep mode + FLITFLPEN : Boolean := True; + -- SRAM 1interface clock enable during Sleep mode + SRAM1LPEN : Boolean := True; + -- unspecified + Reserved_17_20 : HAL.UInt4 := 16#3#; + -- DMA1 clock enable during Sleep mode + DMA1LPEN : Boolean := True; + -- DMA2 clock enable during Sleep mode + DMA2LPEN : Boolean := True; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#FC#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB1LPENR_Register use record + GPIOALPEN at 0 range 0 .. 0; + GPIOBLPEN at 0 range 1 .. 1; + GPIOCLPEN at 0 range 2 .. 2; + GPIODLPEN at 0 range 3 .. 3; + GPIOELPEN at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + GPIOHLPEN at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + CRCLPEN at 0 range 12 .. 12; + Reserved_13_14 at 0 range 13 .. 14; + FLITFLPEN at 0 range 15 .. 15; + SRAM1LPEN at 0 range 16 .. 16; + Reserved_17_20 at 0 range 17 .. 20; + DMA1LPEN at 0 range 21 .. 21; + DMA2LPEN at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- AHB2 peripheral clock enable in low power mode register + type AHB2LPENR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#71#; + -- USB OTG FS clock enable during Sleep mode + OTGFSLPEN : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AHB2LPENR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + OTGFSLPEN at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- APB1 peripheral clock enable in low power mode register + type APB1LPENR_Register is record + -- TIM2 clock enable during Sleep mode + TIM2LPEN : Boolean := True; + -- TIM3 clock enable during Sleep mode + TIM3LPEN : Boolean := True; + -- TIM4 clock enable during Sleep mode + TIM4LPEN : Boolean := True; + -- TIM5 clock enable during Sleep mode + TIM5LPEN : Boolean := True; + -- unspecified + Reserved_4_10 : HAL.UInt7 := 16#1F#; + -- Window watchdog clock enable during Sleep mode + WWDGLPEN : Boolean := True; + -- unspecified + Reserved_12_13 : HAL.UInt2 := 16#0#; + -- SPI2 clock enable during Sleep mode + SPI2LPEN : Boolean := True; + -- SPI3 clock enable during Sleep mode + SPI3LPEN : Boolean := True; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- USART2 clock enable during Sleep mode + USART2LPEN : Boolean := True; + -- unspecified + Reserved_18_20 : HAL.UInt3 := 16#7#; + -- I2C1 clock enable during Sleep mode + I2C1LPEN : Boolean := True; + -- I2C2 clock enable during Sleep mode + I2C2LPEN : Boolean := True; + -- I2C3 clock enable during Sleep mode + I2C3LPEN : Boolean := True; + -- unspecified + Reserved_24_27 : HAL.UInt4 := 16#6#; + -- Power interface clock enable during Sleep mode + PWRLPEN : Boolean := True; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB1LPENR_Register use record + TIM2LPEN at 0 range 0 .. 0; + TIM3LPEN at 0 range 1 .. 1; + TIM4LPEN at 0 range 2 .. 2; + TIM5LPEN at 0 range 3 .. 3; + Reserved_4_10 at 0 range 4 .. 10; + WWDGLPEN at 0 range 11 .. 11; + Reserved_12_13 at 0 range 12 .. 13; + SPI2LPEN at 0 range 14 .. 14; + SPI3LPEN at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + USART2LPEN at 0 range 17 .. 17; + Reserved_18_20 at 0 range 18 .. 20; + I2C1LPEN at 0 range 21 .. 21; + I2C2LPEN at 0 range 22 .. 22; + I2C3LPEN at 0 range 23 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + PWRLPEN at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- APB2 peripheral clock enabled in low power mode register + type APB2LPENR_Register is record + -- TIM1 clock enable during Sleep mode + TIM1LPEN : Boolean := True; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#1#; + -- USART1 clock enable during Sleep mode + USART1LPEN : Boolean := True; + -- USART6 clock enable during Sleep mode + USART6LPEN : Boolean := True; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- ADC1 clock enable during Sleep mode + ADC1LPEN : Boolean := True; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#3#; + -- SDIO clock enable during Sleep mode + SDIOLPEN : Boolean := True; + -- SPI 1 clock enable during Sleep mode + SPI1LPEN : Boolean := True; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- System configuration controller clock enable during Sleep mode + SYSCFGLPEN : Boolean := True; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- TIM9 clock enable during sleep mode + TIM9LPEN : Boolean := True; + -- TIM10 clock enable during Sleep mode + TIM10LPEN : Boolean := True; + -- TIM11 clock enable during Sleep mode + TIM11LPEN : Boolean := True; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APB2LPENR_Register use record + TIM1LPEN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + USART1LPEN at 0 range 4 .. 4; + USART6LPEN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ADC1LPEN at 0 range 8 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + SDIOLPEN at 0 range 11 .. 11; + SPI1LPEN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SYSCFGLPEN at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + TIM9LPEN at 0 range 16 .. 16; + TIM10LPEN at 0 range 17 .. 17; + TIM11LPEN at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- BDCR_RTCSEL array + type BDCR_RTCSEL_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for BDCR_RTCSEL + type BDCR_RTCSEL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RTCSEL as a value + Val : HAL.UInt2; + when True => + -- RTCSEL as an array + Arr : BDCR_RTCSEL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for BDCR_RTCSEL_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Backup domain control register + type BDCR_Register is record + -- External low-speed oscillator enable + LSEON : Boolean := False; + -- Read-only. External low-speed oscillator ready + LSERDY : Boolean := False; + -- External low-speed oscillator bypass + LSEBYP : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- RTC clock source selection + RTCSEL : BDCR_RTCSEL_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_10_14 : HAL.UInt5 := 16#0#; + -- RTC clock enable + RTCEN : Boolean := False; + -- Backup domain software reset + BDRST : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BDCR_Register use record + LSEON at 0 range 0 .. 0; + LSERDY at 0 range 1 .. 1; + LSEBYP at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + RTCSEL at 0 range 8 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + RTCEN at 0 range 15 .. 15; + BDRST at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- clock control & status register + type CSR_Register is record + -- Internal low-speed oscillator enable + LSION : Boolean := False; + -- Read-only. Internal low-speed oscillator ready + LSIRDY : Boolean := False; + -- unspecified + Reserved_2_23 : HAL.UInt22 := 16#0#; + -- Remove reset flag + RMVF : Boolean := False; + -- BOR reset flag + BORRSTF : Boolean := True; + -- PIN reset flag + PADRSTF : Boolean := True; + -- POR/PDR reset flag + PORRSTF : Boolean := True; + -- Software reset flag + SFTRSTF : Boolean := False; + -- Independent watchdog reset flag + WDGRSTF : Boolean := False; + -- Window watchdog reset flag + WWDGRSTF : Boolean := False; + -- Low-power reset flag + LPWRRSTF : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSR_Register use record + LSION at 0 range 0 .. 0; + LSIRDY at 0 range 1 .. 1; + Reserved_2_23 at 0 range 2 .. 23; + RMVF at 0 range 24 .. 24; + BORRSTF at 0 range 25 .. 25; + PADRSTF at 0 range 26 .. 26; + PORRSTF at 0 range 27 .. 27; + SFTRSTF at 0 range 28 .. 28; + WDGRSTF at 0 range 29 .. 29; + WWDGRSTF at 0 range 30 .. 30; + LPWRRSTF at 0 range 31 .. 31; + end record; + + subtype SSCGR_MODPER_Field is HAL.UInt13; + subtype SSCGR_INCSTEP_Field is HAL.UInt15; + + -- spread spectrum clock generation register + type SSCGR_Register is record + -- Modulation period + MODPER : SSCGR_MODPER_Field := 16#0#; + -- Incrementation step + INCSTEP : SSCGR_INCSTEP_Field := 16#0#; + -- unspecified + Reserved_28_29 : HAL.UInt2 := 16#0#; + -- Spread Select + SPREADSEL : Boolean := False; + -- Spread spectrum modulation enable + SSCGEN : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SSCGR_Register use record + MODPER at 0 range 0 .. 12; + INCSTEP at 0 range 13 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + SPREADSEL at 0 range 30 .. 30; + SSCGEN at 0 range 31 .. 31; + end record; + + subtype PLLI2SCFGR_PLLI2SNx_Field is HAL.UInt9; + subtype PLLI2SCFGR_PLLI2SRx_Field is HAL.UInt3; + + -- PLLI2S configuration register + type PLLI2SCFGR_Register is record + -- unspecified + Reserved_0_5 : HAL.UInt6 := 16#0#; + -- PLLI2S multiplication factor for VCO + PLLI2SNx : PLLI2SCFGR_PLLI2SNx_Field := 16#C0#; + -- unspecified + Reserved_15_27 : HAL.UInt13 := 16#0#; + -- PLLI2S division factor for I2S clocks + PLLI2SRx : PLLI2SCFGR_PLLI2SRx_Field := 16#2#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLLI2SCFGR_Register use record + Reserved_0_5 at 0 range 0 .. 5; + PLLI2SNx at 0 range 6 .. 14; + Reserved_15_27 at 0 range 15 .. 27; + PLLI2SRx at 0 range 28 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Reset and clock control + type RCC_Peripheral is record + -- clock control register + CR : aliased CR_Register; + -- PLL configuration register + PLLCFGR : aliased PLLCFGR_Register; + -- clock configuration register + CFGR : aliased CFGR_Register; + -- clock interrupt register + CIR : aliased CIR_Register; + -- AHB1 peripheral reset register + AHB1RSTR : aliased AHB1RSTR_Register; + -- AHB2 peripheral reset register + AHB2RSTR : aliased AHB2RSTR_Register; + -- APB1 peripheral reset register + APB1RSTR : aliased APB1RSTR_Register; + -- APB2 peripheral reset register + APB2RSTR : aliased APB2RSTR_Register; + -- AHB1 peripheral clock register + AHB1ENR : aliased AHB1ENR_Register; + -- AHB2 peripheral clock enable register + AHB2ENR : aliased AHB2ENR_Register; + -- APB1 peripheral clock enable register + APB1ENR : aliased APB1ENR_Register; + -- APB2 peripheral clock enable register + APB2ENR : aliased APB2ENR_Register; + -- AHB1 peripheral clock enable in low power mode register + AHB1LPENR : aliased AHB1LPENR_Register; + -- AHB2 peripheral clock enable in low power mode register + AHB2LPENR : aliased AHB2LPENR_Register; + -- APB1 peripheral clock enable in low power mode register + APB1LPENR : aliased APB1LPENR_Register; + -- APB2 peripheral clock enabled in low power mode register + APB2LPENR : aliased APB2LPENR_Register; + -- Backup domain control register + BDCR : aliased BDCR_Register; + -- clock control & status register + CSR : aliased CSR_Register; + -- spread spectrum clock generation register + SSCGR : aliased SSCGR_Register; + -- PLLI2S configuration register + PLLI2SCFGR : aliased PLLI2SCFGR_Register; + end record + with Volatile; + + for RCC_Peripheral use record + CR at 16#0# range 0 .. 31; + PLLCFGR at 16#4# range 0 .. 31; + CFGR at 16#8# range 0 .. 31; + CIR at 16#C# range 0 .. 31; + AHB1RSTR at 16#10# range 0 .. 31; + AHB2RSTR at 16#14# range 0 .. 31; + APB1RSTR at 16#20# range 0 .. 31; + APB2RSTR at 16#24# range 0 .. 31; + AHB1ENR at 16#30# range 0 .. 31; + AHB2ENR at 16#34# range 0 .. 31; + APB1ENR at 16#40# range 0 .. 31; + APB2ENR at 16#44# range 0 .. 31; + AHB1LPENR at 16#50# range 0 .. 31; + AHB2LPENR at 16#54# range 0 .. 31; + APB1LPENR at 16#60# range 0 .. 31; + APB2LPENR at 16#64# range 0 .. 31; + BDCR at 16#70# range 0 .. 31; + CSR at 16#74# range 0 .. 31; + SSCGR at 16#80# range 0 .. 31; + PLLI2SCFGR at 16#84# range 0 .. 31; + end record; + + -- Reset and clock control + RCC_Periph : aliased RCC_Peripheral + with Import, Address => RCC_Base; + +end STM32_SVD.RCC; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-rtc.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-rtc.ads new file mode 100644 index 000000000..f0fb6538d --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-rtc.ads @@ -0,0 +1,851 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.RTC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype TR_SU_Field is HAL.UInt4; + subtype TR_ST_Field is HAL.UInt3; + subtype TR_MNU_Field is HAL.UInt4; + subtype TR_MNT_Field is HAL.UInt3; + subtype TR_HU_Field is HAL.UInt4; + subtype TR_HT_Field is HAL.UInt2; + + -- time register + type TR_Register is record + -- Second units in BCD format + SU : TR_SU_Field := 16#0#; + -- Second tens in BCD format + ST : TR_ST_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Minute units in BCD format + MNU : TR_MNU_Field := 16#0#; + -- Minute tens in BCD format + MNT : TR_MNT_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Hour units in BCD format + HU : TR_HU_Field := 16#0#; + -- Hour tens in BCD format + HT : TR_HT_Field := 16#0#; + -- AM/PM notation + PM : Boolean := False; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TR_Register use record + SU at 0 range 0 .. 3; + ST at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MNU at 0 range 8 .. 11; + MNT at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HU at 0 range 16 .. 19; + HT at 0 range 20 .. 21; + PM at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype DR_DU_Field is HAL.UInt4; + subtype DR_DT_Field is HAL.UInt2; + subtype DR_MU_Field is HAL.UInt4; + subtype DR_WDU_Field is HAL.UInt3; + subtype DR_YU_Field is HAL.UInt4; + subtype DR_YT_Field is HAL.UInt4; + + -- date register + type DR_Register is record + -- Date units in BCD format + DU : DR_DU_Field := 16#1#; + -- Date tens in BCD format + DT : DR_DT_Field := 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Month units in BCD format + MU : DR_MU_Field := 16#1#; + -- Month tens in BCD format + MT : Boolean := False; + -- Week day units + WDU : DR_WDU_Field := 16#1#; + -- Year units in BCD format + YU : DR_YU_Field := 16#0#; + -- Year tens in BCD format + YT : DR_YT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DR_Register use record + DU at 0 range 0 .. 3; + DT at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + MU at 0 range 8 .. 11; + MT at 0 range 12 .. 12; + WDU at 0 range 13 .. 15; + YU at 0 range 16 .. 19; + YT at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CR_WCKSEL_Field is HAL.UInt3; + subtype CR_OSEL_Field is HAL.UInt2; + + -- control register + type CR_Register is record + -- Wakeup clock selection + WCKSEL : CR_WCKSEL_Field := 16#0#; + -- Time-stamp event active edge + TSEDGE : Boolean := False; + -- Reference clock detection enable (50 or 60 Hz) + REFCKON : Boolean := False; + -- Bypass the shadow registers + BYPSHAD : Boolean := False; + -- Hour format + FMT : Boolean := False; + -- Coarse digital calibration enable + DCE : Boolean := False; + -- Alarm A enable + ALRAE : Boolean := False; + -- Alarm B enable + ALRBE : Boolean := False; + -- Wakeup timer enable + WUTE : Boolean := False; + -- Time stamp enable + TSE : Boolean := False; + -- Alarm A interrupt enable + ALRAIE : Boolean := False; + -- Alarm B interrupt enable + ALRBIE : Boolean := False; + -- Wakeup timer interrupt enable + WUTIE : Boolean := False; + -- Time-stamp interrupt enable + TSIE : Boolean := False; + -- Add 1 hour (summer time change) + ADD1H : Boolean := False; + -- Subtract 1 hour (winter time change) + SUB1H : Boolean := False; + -- Backup + BKP : Boolean := False; + -- Calibration Output selection + COSEL : Boolean := False; + -- Output polarity + POL : Boolean := False; + -- Output selection + OSEL : CR_OSEL_Field := 16#0#; + -- Calibration output enable + COE : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + WCKSEL at 0 range 0 .. 2; + TSEDGE at 0 range 3 .. 3; + REFCKON at 0 range 4 .. 4; + BYPSHAD at 0 range 5 .. 5; + FMT at 0 range 6 .. 6; + DCE at 0 range 7 .. 7; + ALRAE at 0 range 8 .. 8; + ALRBE at 0 range 9 .. 9; + WUTE at 0 range 10 .. 10; + TSE at 0 range 11 .. 11; + ALRAIE at 0 range 12 .. 12; + ALRBIE at 0 range 13 .. 13; + WUTIE at 0 range 14 .. 14; + TSIE at 0 range 15 .. 15; + ADD1H at 0 range 16 .. 16; + SUB1H at 0 range 17 .. 17; + BKP at 0 range 18 .. 18; + COSEL at 0 range 19 .. 19; + POL at 0 range 20 .. 20; + OSEL at 0 range 21 .. 22; + COE at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- initialization and status register + type ISR_Register is record + -- Read-only. Alarm A write flag + ALRAWF : Boolean := True; + -- Read-only. Alarm B write flag + ALRBWF : Boolean := True; + -- Read-only. Wakeup timer write flag + WUTWF : Boolean := True; + -- Shift operation pending + SHPF : Boolean := False; + -- Read-only. Initialization status flag + INITS : Boolean := False; + -- Registers synchronization flag + RSF : Boolean := False; + -- Read-only. Initialization flag + INITF : Boolean := False; + -- Initialization mode + INIT : Boolean := False; + -- Alarm A flag + ALRAF : Boolean := False; + -- Alarm B flag + ALRBF : Boolean := False; + -- Wakeup timer flag + WUTF : Boolean := False; + -- Time-stamp flag + TSF : Boolean := False; + -- Time-stamp overflow flag + TSOVF : Boolean := False; + -- Tamper detection flag + TAMP1F : Boolean := False; + -- TAMPER2 detection flag + TAMP2F : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Read-only. Recalibration pending Flag + RECALPF : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ISR_Register use record + ALRAWF at 0 range 0 .. 0; + ALRBWF at 0 range 1 .. 1; + WUTWF at 0 range 2 .. 2; + SHPF at 0 range 3 .. 3; + INITS at 0 range 4 .. 4; + RSF at 0 range 5 .. 5; + INITF at 0 range 6 .. 6; + INIT at 0 range 7 .. 7; + ALRAF at 0 range 8 .. 8; + ALRBF at 0 range 9 .. 9; + WUTF at 0 range 10 .. 10; + TSF at 0 range 11 .. 11; + TSOVF at 0 range 12 .. 12; + TAMP1F at 0 range 13 .. 13; + TAMP2F at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + RECALPF at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype PRER_PREDIV_S_Field is HAL.UInt15; + subtype PRER_PREDIV_A_Field is HAL.UInt7; + + -- prescaler register + type PRER_Register is record + -- Synchronous prescaler factor + PREDIV_S : PRER_PREDIV_S_Field := 16#FF#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Asynchronous prescaler factor + PREDIV_A : PRER_PREDIV_A_Field := 16#7F#; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRER_Register use record + PREDIV_S at 0 range 0 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PREDIV_A at 0 range 16 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype WUTR_WUT_Field is HAL.UInt16; + + -- wakeup timer register + type WUTR_Register is record + -- Wakeup auto-reload value bits + WUT : WUTR_WUT_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WUTR_Register use record + WUT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CALIBR_DC_Field is HAL.UInt5; + + -- calibration register + type CALIBR_Register is record + -- Digital calibration + DC : CALIBR_DC_Field := 16#0#; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Digital calibration sign + DCS : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CALIBR_Register use record + DC at 0 range 0 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + DCS at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ALRMAR_SU_Field is HAL.UInt4; + subtype ALRMAR_ST_Field is HAL.UInt3; + subtype ALRMAR_MNU_Field is HAL.UInt4; + subtype ALRMAR_MNT_Field is HAL.UInt3; + subtype ALRMAR_HU_Field is HAL.UInt4; + subtype ALRMAR_HT_Field is HAL.UInt2; + subtype ALRMAR_DU_Field is HAL.UInt4; + subtype ALRMAR_DT_Field is HAL.UInt2; + + -- alarm A register + type ALRMAR_Register is record + -- Second units in BCD format + SU : ALRMAR_SU_Field := 16#0#; + -- Second tens in BCD format + ST : ALRMAR_ST_Field := 16#0#; + -- Alarm A seconds mask + MSK1 : Boolean := False; + -- Minute units in BCD format + MNU : ALRMAR_MNU_Field := 16#0#; + -- Minute tens in BCD format + MNT : ALRMAR_MNT_Field := 16#0#; + -- Alarm A minutes mask + MSK2 : Boolean := False; + -- Hour units in BCD format + HU : ALRMAR_HU_Field := 16#0#; + -- Hour tens in BCD format + HT : ALRMAR_HT_Field := 16#0#; + -- AM/PM notation + PM : Boolean := False; + -- Alarm A hours mask + MSK3 : Boolean := False; + -- Date units or day in BCD format + DU : ALRMAR_DU_Field := 16#0#; + -- Date tens in BCD format + DT : ALRMAR_DT_Field := 16#0#; + -- Week day selection + WDSEL : Boolean := False; + -- Alarm A date mask + MSK4 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALRMAR_Register use record + SU at 0 range 0 .. 3; + ST at 0 range 4 .. 6; + MSK1 at 0 range 7 .. 7; + MNU at 0 range 8 .. 11; + MNT at 0 range 12 .. 14; + MSK2 at 0 range 15 .. 15; + HU at 0 range 16 .. 19; + HT at 0 range 20 .. 21; + PM at 0 range 22 .. 22; + MSK3 at 0 range 23 .. 23; + DU at 0 range 24 .. 27; + DT at 0 range 28 .. 29; + WDSEL at 0 range 30 .. 30; + MSK4 at 0 range 31 .. 31; + end record; + + subtype ALRMBR_SU_Field is HAL.UInt4; + subtype ALRMBR_ST_Field is HAL.UInt3; + subtype ALRMBR_MNU_Field is HAL.UInt4; + subtype ALRMBR_MNT_Field is HAL.UInt3; + subtype ALRMBR_HU_Field is HAL.UInt4; + subtype ALRMBR_HT_Field is HAL.UInt2; + subtype ALRMBR_DU_Field is HAL.UInt4; + subtype ALRMBR_DT_Field is HAL.UInt2; + + -- alarm B register + type ALRMBR_Register is record + -- Second units in BCD format + SU : ALRMBR_SU_Field := 16#0#; + -- Second tens in BCD format + ST : ALRMBR_ST_Field := 16#0#; + -- Alarm B seconds mask + MSK1 : Boolean := False; + -- Minute units in BCD format + MNU : ALRMBR_MNU_Field := 16#0#; + -- Minute tens in BCD format + MNT : ALRMBR_MNT_Field := 16#0#; + -- Alarm B minutes mask + MSK2 : Boolean := False; + -- Hour units in BCD format + HU : ALRMBR_HU_Field := 16#0#; + -- Hour tens in BCD format + HT : ALRMBR_HT_Field := 16#0#; + -- AM/PM notation + PM : Boolean := False; + -- Alarm B hours mask + MSK3 : Boolean := False; + -- Date units or day in BCD format + DU : ALRMBR_DU_Field := 16#0#; + -- Date tens in BCD format + DT : ALRMBR_DT_Field := 16#0#; + -- Week day selection + WDSEL : Boolean := False; + -- Alarm B date mask + MSK4 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALRMBR_Register use record + SU at 0 range 0 .. 3; + ST at 0 range 4 .. 6; + MSK1 at 0 range 7 .. 7; + MNU at 0 range 8 .. 11; + MNT at 0 range 12 .. 14; + MSK2 at 0 range 15 .. 15; + HU at 0 range 16 .. 19; + HT at 0 range 20 .. 21; + PM at 0 range 22 .. 22; + MSK3 at 0 range 23 .. 23; + DU at 0 range 24 .. 27; + DT at 0 range 28 .. 29; + WDSEL at 0 range 30 .. 30; + MSK4 at 0 range 31 .. 31; + end record; + + subtype WPR_KEY_Field is HAL.UInt8; + + -- write protection register + type WPR_Register is record + -- Write-only. Write protection key + KEY : WPR_KEY_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WPR_Register use record + KEY at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype SSR_SS_Field is HAL.UInt16; + + -- sub second register + type SSR_Register is record + -- Read-only. Sub second value + SS : SSR_SS_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SSR_Register use record + SS at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SHIFTR_SUBFS_Field is HAL.UInt15; + + -- shift control register + type SHIFTR_Register is record + -- Write-only. Subtract a fraction of a second + SUBFS : SHIFTR_SUBFS_Field := 16#0#; + -- unspecified + Reserved_15_30 : HAL.UInt16 := 16#0#; + -- Write-only. Add one second + ADD1S : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHIFTR_Register use record + SUBFS at 0 range 0 .. 14; + Reserved_15_30 at 0 range 15 .. 30; + ADD1S at 0 range 31 .. 31; + end record; + + subtype TSTR_SU_Field is HAL.UInt4; + subtype TSTR_ST_Field is HAL.UInt3; + subtype TSTR_MNU_Field is HAL.UInt4; + subtype TSTR_MNT_Field is HAL.UInt3; + subtype TSTR_HU_Field is HAL.UInt4; + subtype TSTR_HT_Field is HAL.UInt2; + + -- time stamp time register + type TSTR_Register is record + -- Read-only. Second units in BCD format + SU : TSTR_SU_Field; + -- Read-only. Second tens in BCD format + ST : TSTR_ST_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Minute units in BCD format + MNU : TSTR_MNU_Field; + -- Read-only. Minute tens in BCD format + MNT : TSTR_MNT_Field; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. Hour units in BCD format + HU : TSTR_HU_Field; + -- Read-only. Hour tens in BCD format + HT : TSTR_HT_Field; + -- Read-only. AM/PM notation + PM : Boolean; + -- unspecified + Reserved_23_31 : HAL.UInt9; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TSTR_Register use record + SU at 0 range 0 .. 3; + ST at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MNU at 0 range 8 .. 11; + MNT at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HU at 0 range 16 .. 19; + HT at 0 range 20 .. 21; + PM at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype TSDR_DU_Field is HAL.UInt4; + subtype TSDR_DT_Field is HAL.UInt2; + subtype TSDR_MU_Field is HAL.UInt4; + subtype TSDR_WDU_Field is HAL.UInt3; + + -- time stamp date register + type TSDR_Register is record + -- Read-only. Date units in BCD format + DU : TSDR_DU_Field; + -- Read-only. Date tens in BCD format + DT : TSDR_DT_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Month units in BCD format + MU : TSDR_MU_Field; + -- Read-only. Month tens in BCD format + MT : Boolean; + -- Read-only. Week day units + WDU : TSDR_WDU_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TSDR_Register use record + DU at 0 range 0 .. 3; + DT at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + MU at 0 range 8 .. 11; + MT at 0 range 12 .. 12; + WDU at 0 range 13 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TSSSR_SS_Field is HAL.UInt16; + + -- timestamp sub second register + type TSSSR_Register is record + -- Read-only. Sub second value + SS : TSSSR_SS_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TSSSR_Register use record + SS at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CALR_CALM_Field is HAL.UInt9; + + -- calibration register + type CALR_Register is record + -- Calibration minus + CALM : CALR_CALM_Field := 16#0#; + -- unspecified + Reserved_9_12 : HAL.UInt4 := 16#0#; + -- Use a 16-second calibration cycle period + CALW16 : Boolean := False; + -- Use an 8-second calibration cycle period + CALW8 : Boolean := False; + -- Increase frequency of RTC by 488.5 ppm + CALP : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CALR_Register use record + CALM at 0 range 0 .. 8; + Reserved_9_12 at 0 range 9 .. 12; + CALW16 at 0 range 13 .. 13; + CALW8 at 0 range 14 .. 14; + CALP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TAFCR_TAMPFREQ_Field is HAL.UInt3; + subtype TAFCR_TAMPFLT_Field is HAL.UInt2; + subtype TAFCR_TAMPPRCH_Field is HAL.UInt2; + + -- tamper and alternate function configuration register + type TAFCR_Register is record + -- Tamper 1 detection enable + TAMP1E : Boolean := False; + -- Active level for tamper 1 + TAMP1TRG : Boolean := False; + -- Tamper interrupt enable + TAMPIE : Boolean := False; + -- Tamper 2 detection enable + TAMP2E : Boolean := False; + -- Active level for tamper 2 + TAMP2TRG : Boolean := False; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Activate timestamp on tamper detection event + TAMPTS : Boolean := False; + -- Tamper sampling frequency + TAMPFREQ : TAFCR_TAMPFREQ_Field := 16#0#; + -- Tamper filter count + TAMPFLT : TAFCR_TAMPFLT_Field := 16#0#; + -- Tamper precharge duration + TAMPPRCH : TAFCR_TAMPPRCH_Field := 16#0#; + -- TAMPER pull-up disable + TAMPPUDIS : Boolean := False; + -- TAMPER1 mapping + TAMP1INSEL : Boolean := False; + -- TIMESTAMP mapping + TSINSEL : Boolean := False; + -- AFO_ALARM output type + ALARMOUTTYPE : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TAFCR_Register use record + TAMP1E at 0 range 0 .. 0; + TAMP1TRG at 0 range 1 .. 1; + TAMPIE at 0 range 2 .. 2; + TAMP2E at 0 range 3 .. 3; + TAMP2TRG at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + TAMPTS at 0 range 7 .. 7; + TAMPFREQ at 0 range 8 .. 10; + TAMPFLT at 0 range 11 .. 12; + TAMPPRCH at 0 range 13 .. 14; + TAMPPUDIS at 0 range 15 .. 15; + TAMP1INSEL at 0 range 16 .. 16; + TSINSEL at 0 range 17 .. 17; + ALARMOUTTYPE at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype ALRMASSR_SS_Field is HAL.UInt15; + subtype ALRMASSR_MASKSS_Field is HAL.UInt4; + + -- alarm A sub second register + type ALRMASSR_Register is record + -- Sub seconds value + SS : ALRMASSR_SS_Field := 16#0#; + -- unspecified + Reserved_15_23 : HAL.UInt9 := 16#0#; + -- Mask the most-significant bits starting at this bit + MASKSS : ALRMASSR_MASKSS_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALRMASSR_Register use record + SS at 0 range 0 .. 14; + Reserved_15_23 at 0 range 15 .. 23; + MASKSS at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ALRMBSSR_SS_Field is HAL.UInt15; + subtype ALRMBSSR_MASKSS_Field is HAL.UInt4; + + -- alarm B sub second register + type ALRMBSSR_Register is record + -- Sub seconds value + SS : ALRMBSSR_SS_Field := 16#0#; + -- unspecified + Reserved_15_23 : HAL.UInt9 := 16#0#; + -- Mask the most-significant bits starting at this bit + MASKSS : ALRMBSSR_MASKSS_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALRMBSSR_Register use record + SS at 0 range 0 .. 14; + Reserved_15_23 at 0 range 15 .. 23; + MASKSS at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Real-time clock + type RTC_Peripheral is record + -- time register + TR : aliased TR_Register; + -- date register + DR : aliased DR_Register; + -- control register + CR : aliased CR_Register; + -- initialization and status register + ISR : aliased ISR_Register; + -- prescaler register + PRER : aliased PRER_Register; + -- wakeup timer register + WUTR : aliased WUTR_Register; + -- calibration register + CALIBR : aliased CALIBR_Register; + -- alarm A register + ALRMAR : aliased ALRMAR_Register; + -- alarm B register + ALRMBR : aliased ALRMBR_Register; + -- write protection register + WPR : aliased WPR_Register; + -- sub second register + SSR : aliased SSR_Register; + -- shift control register + SHIFTR : aliased SHIFTR_Register; + -- time stamp time register + TSTR : aliased TSTR_Register; + -- time stamp date register + TSDR : aliased TSDR_Register; + -- timestamp sub second register + TSSSR : aliased TSSSR_Register; + -- calibration register + CALR : aliased CALR_Register; + -- tamper and alternate function configuration register + TAFCR : aliased TAFCR_Register; + -- alarm A sub second register + ALRMASSR : aliased ALRMASSR_Register; + -- alarm B sub second register + ALRMBSSR : aliased ALRMBSSR_Register; + -- backup register + BKP0R : aliased HAL.UInt32; + -- backup register + BKP1R : aliased HAL.UInt32; + -- backup register + BKP2R : aliased HAL.UInt32; + -- backup register + BKP3R : aliased HAL.UInt32; + -- backup register + BKP4R : aliased HAL.UInt32; + -- backup register + BKP5R : aliased HAL.UInt32; + -- backup register + BKP6R : aliased HAL.UInt32; + -- backup register + BKP7R : aliased HAL.UInt32; + -- backup register + BKP8R : aliased HAL.UInt32; + -- backup register + BKP9R : aliased HAL.UInt32; + -- backup register + BKP10R : aliased HAL.UInt32; + -- backup register + BKP11R : aliased HAL.UInt32; + -- backup register + BKP12R : aliased HAL.UInt32; + -- backup register + BKP13R : aliased HAL.UInt32; + -- backup register + BKP14R : aliased HAL.UInt32; + -- backup register + BKP15R : aliased HAL.UInt32; + -- backup register + BKP16R : aliased HAL.UInt32; + -- backup register + BKP17R : aliased HAL.UInt32; + -- backup register + BKP18R : aliased HAL.UInt32; + -- backup register + BKP19R : aliased HAL.UInt32; + end record + with Volatile; + + for RTC_Peripheral use record + TR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; + ISR at 16#C# range 0 .. 31; + PRER at 16#10# range 0 .. 31; + WUTR at 16#14# range 0 .. 31; + CALIBR at 16#18# range 0 .. 31; + ALRMAR at 16#1C# range 0 .. 31; + ALRMBR at 16#20# range 0 .. 31; + WPR at 16#24# range 0 .. 31; + SSR at 16#28# range 0 .. 31; + SHIFTR at 16#2C# range 0 .. 31; + TSTR at 16#30# range 0 .. 31; + TSDR at 16#34# range 0 .. 31; + TSSSR at 16#38# range 0 .. 31; + CALR at 16#3C# range 0 .. 31; + TAFCR at 16#40# range 0 .. 31; + ALRMASSR at 16#44# range 0 .. 31; + ALRMBSSR at 16#48# range 0 .. 31; + BKP0R at 16#50# range 0 .. 31; + BKP1R at 16#54# range 0 .. 31; + BKP2R at 16#58# range 0 .. 31; + BKP3R at 16#5C# range 0 .. 31; + BKP4R at 16#60# range 0 .. 31; + BKP5R at 16#64# range 0 .. 31; + BKP6R at 16#68# range 0 .. 31; + BKP7R at 16#6C# range 0 .. 31; + BKP8R at 16#70# range 0 .. 31; + BKP9R at 16#74# range 0 .. 31; + BKP10R at 16#78# range 0 .. 31; + BKP11R at 16#7C# range 0 .. 31; + BKP12R at 16#80# range 0 .. 31; + BKP13R at 16#84# range 0 .. 31; + BKP14R at 16#88# range 0 .. 31; + BKP15R at 16#8C# range 0 .. 31; + BKP16R at 16#90# range 0 .. 31; + BKP17R at 16#94# range 0 .. 31; + BKP18R at 16#98# range 0 .. 31; + BKP19R at 16#9C# range 0 .. 31; + end record; + + -- Real-time clock + RTC_Periph : aliased RTC_Peripheral + with Import, Address => RTC_Base; + +end STM32_SVD.RTC; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-scb.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-scb.ads new file mode 100644 index 000000000..134f5685a --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-scb.ads @@ -0,0 +1,554 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.SCB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CPUID_Revision_Field is HAL.UInt4; + subtype CPUID_PartNo_Field is HAL.UInt12; + subtype CPUID_Constant_Field is HAL.UInt4; + subtype CPUID_Variant_Field is HAL.UInt4; + subtype CPUID_Implementer_Field is HAL.UInt8; + + -- CPUID base register + type CPUID_Register is record + -- Read-only. Revision number + Revision : CPUID_Revision_Field; + -- Read-only. Part number of the processor + PartNo : CPUID_PartNo_Field; + -- Read-only. Reads as 0xF + Constant_k : CPUID_Constant_Field; + -- Read-only. Variant number + Variant : CPUID_Variant_Field; + -- Read-only. Implementer code + Implementer : CPUID_Implementer_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPUID_Register use record + Revision at 0 range 0 .. 3; + PartNo at 0 range 4 .. 15; + Constant_k at 0 range 16 .. 19; + Variant at 0 range 20 .. 23; + Implementer at 0 range 24 .. 31; + end record; + + subtype ICSR_VECTACTIVE_Field is HAL.UInt9; + subtype ICSR_VECTPENDING_Field is HAL.UInt7; + + -- Interrupt control and state register + type ICSR_Register is record + -- Active vector + VECTACTIVE : ICSR_VECTACTIVE_Field := 16#0#; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- Return to base level + RETTOBASE : Boolean := False; + -- Pending vector + VECTPENDING : ICSR_VECTPENDING_Field := 16#0#; + -- unspecified + Reserved_19_21 : HAL.UInt3 := 16#0#; + -- Interrupt pending flag + ISRPENDING : Boolean := False; + -- unspecified + Reserved_23_24 : HAL.UInt2 := 16#0#; + -- SysTick exception clear-pending bit + PENDSTCLR : Boolean := False; + -- SysTick exception set-pending bit + PENDSTSET : Boolean := False; + -- PendSV clear-pending bit + PENDSVCLR : Boolean := False; + -- PendSV set-pending bit + PENDSVSET : Boolean := False; + -- unspecified + Reserved_29_30 : HAL.UInt2 := 16#0#; + -- NMI set-pending bit. + NMIPENDSET : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICSR_Register use record + VECTACTIVE at 0 range 0 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + RETTOBASE at 0 range 11 .. 11; + VECTPENDING at 0 range 12 .. 18; + Reserved_19_21 at 0 range 19 .. 21; + ISRPENDING at 0 range 22 .. 22; + Reserved_23_24 at 0 range 23 .. 24; + PENDSTCLR at 0 range 25 .. 25; + PENDSTSET at 0 range 26 .. 26; + PENDSVCLR at 0 range 27 .. 27; + PENDSVSET at 0 range 28 .. 28; + Reserved_29_30 at 0 range 29 .. 30; + NMIPENDSET at 0 range 31 .. 31; + end record; + + subtype VTOR_TBLOFF_Field is HAL.UInt21; + + -- Vector table offset register + type VTOR_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9 := 16#0#; + -- Vector table base offset field + TBLOFF : VTOR_TBLOFF_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VTOR_Register use record + Reserved_0_8 at 0 range 0 .. 8; + TBLOFF at 0 range 9 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype AIRCR_PRIGROUP_Field is HAL.UInt3; + subtype AIRCR_VECTKEYSTAT_Field is HAL.UInt16; + + -- Application interrupt and reset control register + type AIRCR_Register is record + -- VECTRESET + VECTRESET : Boolean := False; + -- VECTCLRACTIVE + VECTCLRACTIVE : Boolean := False; + -- SYSRESETREQ + SYSRESETREQ : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- PRIGROUP + PRIGROUP : AIRCR_PRIGROUP_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- ENDIANESS + ENDIANESS : Boolean := False; + -- Register key + VECTKEYSTAT : AIRCR_VECTKEYSTAT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AIRCR_Register use record + VECTRESET at 0 range 0 .. 0; + VECTCLRACTIVE at 0 range 1 .. 1; + SYSRESETREQ at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + PRIGROUP at 0 range 8 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + ENDIANESS at 0 range 15 .. 15; + VECTKEYSTAT at 0 range 16 .. 31; + end record; + + -- System control register + type SCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- SLEEPONEXIT + SLEEPONEXIT : Boolean := False; + -- SLEEPDEEP + SLEEPDEEP : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Send Event on Pending bit + SEVEONPEND : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SLEEPONEXIT at 0 range 1 .. 1; + SLEEPDEEP at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SEVEONPEND at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Configuration and control register + type CCR_Register is record + -- Configures how the processor enters Thread mode + NONBASETHRDENA : Boolean := False; + -- USERSETMPEND + USERSETMPEND : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- UNALIGN_ TRP + UNALIGN_TRP : Boolean := False; + -- DIV_0_TRP + DIV_0_TRP : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- BFHFNMIGN + BFHFNMIGN : Boolean := False; + -- STKALIGN + STKALIGN : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR_Register use record + NONBASETHRDENA at 0 range 0 .. 0; + USERSETMPEND at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + UNALIGN_TRP at 0 range 3 .. 3; + DIV_0_TRP at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + BFHFNMIGN at 0 range 8 .. 8; + STKALIGN at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype SHPR1_PRI_4_Field is HAL.UInt8; + subtype SHPR1_PRI_5_Field is HAL.UInt8; + subtype SHPR1_PRI_6_Field is HAL.UInt8; + + -- System handler priority registers + type SHPR1_Register is record + -- Priority of system handler 4 + PRI_4 : SHPR1_PRI_4_Field := 16#0#; + -- Priority of system handler 5 + PRI_5 : SHPR1_PRI_5_Field := 16#0#; + -- Priority of system handler 6 + PRI_6 : SHPR1_PRI_6_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR1_Register use record + PRI_4 at 0 range 0 .. 7; + PRI_5 at 0 range 8 .. 15; + PRI_6 at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SHPR2_PRI_11_Field is HAL.UInt8; + + -- System handler priority registers + type SHPR2_Register is record + -- unspecified + Reserved_0_23 : HAL.UInt24 := 16#0#; + -- Priority of system handler 11 + PRI_11 : SHPR2_PRI_11_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR2_Register use record + Reserved_0_23 at 0 range 0 .. 23; + PRI_11 at 0 range 24 .. 31; + end record; + + subtype SHPR3_PRI_14_Field is HAL.UInt8; + subtype SHPR3_PRI_15_Field is HAL.UInt8; + + -- System handler priority registers + type SHPR3_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Priority of system handler 14 + PRI_14 : SHPR3_PRI_14_Field := 16#0#; + -- Priority of system handler 15 + PRI_15 : SHPR3_PRI_15_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR3_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PRI_14 at 0 range 16 .. 23; + PRI_15 at 0 range 24 .. 31; + end record; + + -- System handler control and state register + type SHCRS_Register is record + -- Memory management fault exception active bit + MEMFAULTACT : Boolean := False; + -- Bus fault exception active bit + BUSFAULTACT : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Usage fault exception active bit + USGFAULTACT : Boolean := False; + -- unspecified + Reserved_4_6 : HAL.UInt3 := 16#0#; + -- SVC call active bit + SVCALLACT : Boolean := False; + -- Debug monitor active bit + MONITORACT : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- PendSV exception active bit + PENDSVACT : Boolean := False; + -- SysTick exception active bit + SYSTICKACT : Boolean := False; + -- Usage fault exception pending bit + USGFAULTPENDED : Boolean := False; + -- Memory management fault exception pending bit + MEMFAULTPENDED : Boolean := False; + -- Bus fault exception pending bit + BUSFAULTPENDED : Boolean := False; + -- SVC call pending bit + SVCALLPENDED : Boolean := False; + -- Memory management fault enable bit + MEMFAULTENA : Boolean := False; + -- Bus fault enable bit + BUSFAULTENA : Boolean := False; + -- Usage fault enable bit + USGFAULTENA : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHCRS_Register use record + MEMFAULTACT at 0 range 0 .. 0; + BUSFAULTACT at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + USGFAULTACT at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + SVCALLACT at 0 range 7 .. 7; + MONITORACT at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PENDSVACT at 0 range 10 .. 10; + SYSTICKACT at 0 range 11 .. 11; + USGFAULTPENDED at 0 range 12 .. 12; + MEMFAULTPENDED at 0 range 13 .. 13; + BUSFAULTPENDED at 0 range 14 .. 14; + SVCALLPENDED at 0 range 15 .. 15; + MEMFAULTENA at 0 range 16 .. 16; + BUSFAULTENA at 0 range 17 .. 17; + USGFAULTENA at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Configurable fault status register + type CFSR_UFSR_BFSR_MMFSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Instruction access violation flag + IACCVIOL : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Memory manager fault on unstacking for a return from exception + MUNSTKERR : Boolean := False; + -- Memory manager fault on stacking for exception entry. + MSTKERR : Boolean := False; + -- MLSPERR + MLSPERR : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Memory Management Fault Address Register (MMAR) valid flag + MMARVALID : Boolean := False; + -- Instruction bus error + IBUSERR : Boolean := False; + -- Precise data bus error + PRECISERR : Boolean := False; + -- Imprecise data bus error + IMPRECISERR : Boolean := False; + -- Bus fault on unstacking for a return from exception + UNSTKERR : Boolean := False; + -- Bus fault on stacking for exception entry + STKERR : Boolean := False; + -- Bus fault on floating-point lazy state preservation + LSPERR : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Bus Fault Address Register (BFAR) valid flag + BFARVALID : Boolean := False; + -- Undefined instruction usage fault + UNDEFINSTR : Boolean := False; + -- Invalid state usage fault + INVSTATE : Boolean := False; + -- Invalid PC load usage fault + INVPC : Boolean := False; + -- No coprocessor usage fault. + NOCP : Boolean := False; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Unaligned access usage fault + UNALIGNED : Boolean := False; + -- Divide by zero usage fault + DIVBYZERO : Boolean := False; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFSR_UFSR_BFSR_MMFSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + IACCVIOL at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MUNSTKERR at 0 range 3 .. 3; + MSTKERR at 0 range 4 .. 4; + MLSPERR at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + MMARVALID at 0 range 7 .. 7; + IBUSERR at 0 range 8 .. 8; + PRECISERR at 0 range 9 .. 9; + IMPRECISERR at 0 range 10 .. 10; + UNSTKERR at 0 range 11 .. 11; + STKERR at 0 range 12 .. 12; + LSPERR at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + BFARVALID at 0 range 15 .. 15; + UNDEFINSTR at 0 range 16 .. 16; + INVSTATE at 0 range 17 .. 17; + INVPC at 0 range 18 .. 18; + NOCP at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + UNALIGNED at 0 range 24 .. 24; + DIVBYZERO at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Hard fault status register + type HFSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Vector table hard fault + VECTTBL : Boolean := False; + -- unspecified + Reserved_2_29 : HAL.UInt28 := 16#0#; + -- Forced hard fault + FORCED : Boolean := False; + -- Reserved for Debug use + DEBUG_VT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTTBL at 0 range 1 .. 1; + Reserved_2_29 at 0 range 2 .. 29; + FORCED at 0 range 30 .. 30; + DEBUG_VT at 0 range 31 .. 31; + end record; + + -- Auxiliary control register + type ACTRL_Register is record + -- DISMCYCINT + DISMCYCINT : Boolean := False; + -- DISDEFWBUF + DISDEFWBUF : Boolean := False; + -- DISFOLD + DISFOLD : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- DISFPCA + DISFPCA : Boolean := False; + -- DISOOFP + DISOOFP : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACTRL_Register use record + DISMCYCINT at 0 range 0 .. 0; + DISDEFWBUF at 0 range 1 .. 1; + DISFOLD at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + DISFPCA at 0 range 8 .. 8; + DISOOFP at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- System control block + type SCB_Peripheral is record + -- CPUID base register + CPUID : aliased CPUID_Register; + -- Interrupt control and state register + ICSR : aliased ICSR_Register; + -- Vector table offset register + VTOR : aliased VTOR_Register; + -- Application interrupt and reset control register + AIRCR : aliased AIRCR_Register; + -- System control register + SCR : aliased SCR_Register; + -- Configuration and control register + CCR : aliased CCR_Register; + -- System handler priority registers + SHPR1 : aliased SHPR1_Register; + -- System handler priority registers + SHPR2 : aliased SHPR2_Register; + -- System handler priority registers + SHPR3 : aliased SHPR3_Register; + -- System handler control and state register + SHCRS : aliased SHCRS_Register; + -- Configurable fault status register + CFSR_UFSR_BFSR_MMFSR : aliased CFSR_UFSR_BFSR_MMFSR_Register; + -- Hard fault status register + HFSR : aliased HFSR_Register; + -- Memory management fault address register + MMFAR : aliased HAL.UInt32; + -- Bus fault address register + BFAR : aliased HAL.UInt32; + -- Auxiliary fault status register + AFSR : aliased HAL.UInt32; + end record + with Volatile; + + for SCB_Peripheral use record + CPUID at 16#0# range 0 .. 31; + ICSR at 16#4# range 0 .. 31; + VTOR at 16#8# range 0 .. 31; + AIRCR at 16#C# range 0 .. 31; + SCR at 16#10# range 0 .. 31; + CCR at 16#14# range 0 .. 31; + SHPR1 at 16#18# range 0 .. 31; + SHPR2 at 16#1C# range 0 .. 31; + SHPR3 at 16#20# range 0 .. 31; + SHCRS at 16#24# range 0 .. 31; + CFSR_UFSR_BFSR_MMFSR at 16#28# range 0 .. 31; + HFSR at 16#2C# range 0 .. 31; + MMFAR at 16#34# range 0 .. 31; + BFAR at 16#38# range 0 .. 31; + AFSR at 16#3C# range 0 .. 31; + end record; + + -- System control block + SCB_Periph : aliased SCB_Peripheral + with Import, Address => SCB_Base; + + -- System control block ACTLR + type SCB_ACTRL_Peripheral is record + -- Auxiliary control register + ACTRL : aliased ACTRL_Register; + end record + with Volatile; + + for SCB_ACTRL_Peripheral use record + ACTRL at 0 range 0 .. 31; + end record; + + -- System control block ACTLR + SCB_ACTRL_Periph : aliased SCB_ACTRL_Peripheral + with Import, Address => SCB_ACTRL_Base; + +end STM32_SVD.SCB; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-sdio.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-sdio.ads new file mode 100644 index 000000000..350a83ceb --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-sdio.ads @@ -0,0 +1,635 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.SDIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- PWRCTRL + type POWER_PWRCTRL_Field is + (-- The clock to card is stopped. + Power_Off, + -- The card is clocked. + Power_On) + with Size => 2; + for POWER_PWRCTRL_Field use + (Power_Off => 0, + Power_On => 3); + + -- power control register + type POWER_Register is record + -- PWRCTRL + PWRCTRL : POWER_PWRCTRL_Field := STM32_SVD.SDIO.Power_Off; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWER_Register use record + PWRCTRL at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype CLKCR_CLKDIV_Field is HAL.UInt8; + + -- Wide bus mode enable bit + type CLKCR_WIDBUS_Field is + (-- Default bus mode: SDMMC_D0 is used. + Bus_Wide_1b, + -- 4-wide bus mode: SDMMC_D[3:0] used. + Bus_Wide_4b, + -- 8-wide bus mode: SDMMC_D[7:0] used. + Bus_Wide_8b) + with Size => 2; + for CLKCR_WIDBUS_Field use + (Bus_Wide_1b => 0, + Bus_Wide_4b => 1, + Bus_Wide_8b => 2); + + -- SDIO_CK dephasing selection bit + type CLKCR_NEGEDGE_Field is + (-- Cmd and Data changed on the SDMMCCLK falling edge succeeding the rising +-- edge of SDMMC_CK. + Edge_Rising, + -- Cmd and Data changed on the SDMMC_CK falling edge. + Edge_Falling) + with Size => 1; + for CLKCR_NEGEDGE_Field use + (Edge_Rising => 0, + Edge_Falling => 1); + + -- SDI clock control register + type CLKCR_Register is record + -- Clock divide factor + CLKDIV : CLKCR_CLKDIV_Field := 16#0#; + -- Clock enable bit + CLKEN : Boolean := False; + -- Power saving configuration bit + PWRSAV : Boolean := False; + -- Clock divider bypass enable bit + BYPASS : Boolean := False; + -- Wide bus mode enable bit + WIDBUS : CLKCR_WIDBUS_Field := STM32_SVD.SDIO.Bus_Wide_1b; + -- SDIO_CK dephasing selection bit + NEGEDGE : CLKCR_NEGEDGE_Field := STM32_SVD.SDIO.Edge_Rising; + -- HW Flow Control enable + HWFC_EN : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLKCR_Register use record + CLKDIV at 0 range 0 .. 7; + CLKEN at 0 range 8 .. 8; + PWRSAV at 0 range 9 .. 9; + BYPASS at 0 range 10 .. 10; + WIDBUS at 0 range 11 .. 12; + NEGEDGE at 0 range 13 .. 13; + HWFC_EN at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype CMD_CMDINDEX_Field is HAL.UInt6; + + -- Wait for response bits + type CMD_WAITRESP_Field is + (-- No response, expect CMDSENT flag. + No_Response, + -- Short response, expect CMDREND or CCRCFAIL flag. + Short_Response, + -- Long response, expect CMDREND or CCRCFAIL flag. + Long_Response) + with Size => 2; + for CMD_WAITRESP_Field use + (No_Response => 0, + Short_Response => 1, + Long_Response => 3); + + -- command register + type CMD_Register is record + -- Command index + CMDINDEX : CMD_CMDINDEX_Field := 16#0#; + -- Wait for response bits + WAITRESP : CMD_WAITRESP_Field := STM32_SVD.SDIO.No_Response; + -- CPSM waits for interrupt request + WAITINT : Boolean := False; + -- CPSM Waits for ends of data transfer (CmdPend internal signal). + WAITPEND : Boolean := False; + -- Command path state machine (CPSM) Enable bit + CPSMEN : Boolean := False; + -- SD I/O suspend command + SDIOSuspend : Boolean := False; + -- Enable CMD completion + ENCMDcompl : Boolean := False; + -- not Interrupt Enable + nIEN : Boolean := False; + -- CE-ATA command + CE_ATACMD : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CMD_Register use record + CMDINDEX at 0 range 0 .. 5; + WAITRESP at 0 range 6 .. 7; + WAITINT at 0 range 8 .. 8; + WAITPEND at 0 range 9 .. 9; + CPSMEN at 0 range 10 .. 10; + SDIOSuspend at 0 range 11 .. 11; + ENCMDcompl at 0 range 12 .. 12; + nIEN at 0 range 13 .. 13; + CE_ATACMD at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype RESPCMD_RESPCMD_Field is HAL.UInt6; + + -- command response register + type RESPCMD_Register is record + -- Read-only. Response command index + RESPCMD : RESPCMD_RESPCMD_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESPCMD_Register use record + RESPCMD at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype DLEN_DATALENGTH_Field is HAL.UInt25; + + -- data length register + type DLEN_Register is record + -- Data length value + DATALENGTH : DLEN_DATALENGTH_Field := 16#0#; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DLEN_Register use record + DATALENGTH at 0 range 0 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Data transfer direction selection + type DCTRL_DTDIR_Field is + (-- Data is sent to the card + Controller_To_Card, + -- Data is read from the card + Card_To_Controller) + with Size => 1; + for DCTRL_DTDIR_Field use + (Controller_To_Card => 0, + Card_To_Controller => 1); + + -- Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + type DCTRL_DTMODE_Field is + (-- Block data transfer + Block, + -- Stream or SDIO multibyte data transfer + Stream) + with Size => 1; + for DCTRL_DTMODE_Field use + (Block => 0, + Stream => 1); + + -- Data block size + type DCTRL_DBLOCKSIZE_Field is + (-- Block length = 2**0 = 1 byte + Block_1B, + -- Block length = 2**1 = 2 byte + Block_2B, + -- Block length = 2**2 = 4 byte + Block_4B, + -- Block length = 2**3 = 8 byte + Block_8B, + -- Block length = 2**4 = 16 byte + Block_16B, + -- Block length = 2**5 = 32 byte + Block_32B, + -- Block length = 2**6 = 64 byte + Block_64B, + -- Block length = 2**7 = 128 byte + Block_128B, + -- Block length = 2**8 = 256 byte + Block_256B, + -- Block length = 2**9 = 512 byte + Block_512B, + -- Block length = 2**10 = 1024 byte + Block_1024B, + -- Block length = 2**11 = 2048 byte + Block_2048B, + -- Block length = 2**12 = 4096 byte + Block_4096B, + -- Block length = 2**13 = 8192 byte + Block_8192B, + -- Block length = 2**14 = 16384 byte + Block_16384B) + with Size => 4; + for DCTRL_DBLOCKSIZE_Field use + (Block_1B => 0, + Block_2B => 1, + Block_4B => 2, + Block_8B => 3, + Block_16B => 4, + Block_32B => 5, + Block_64B => 6, + Block_128B => 7, + Block_256B => 8, + Block_512B => 9, + Block_1024B => 10, + Block_2048B => 11, + Block_4096B => 12, + Block_8192B => 13, + Block_16384B => 14); + + -- data control register + type DCTRL_Register is record + -- DTEN + DTEN : Boolean := False; + -- Data transfer direction selection + DTDIR : DCTRL_DTDIR_Field := STM32_SVD.SDIO.Controller_To_Card; + -- Data transfer mode selection 1: Stream or SDIO multibyte data + -- transfer. + DTMODE : DCTRL_DTMODE_Field := STM32_SVD.SDIO.Block; + -- DMA enable bit + DMAEN : Boolean := False; + -- Data block size + DBLOCKSIZE : DCTRL_DBLOCKSIZE_Field := STM32_SVD.SDIO.Block_1B; + -- Read wait start + RWSTART : Boolean := False; + -- Read wait stop + RWSTOP : Boolean := False; + -- Read wait mode + RWMOD : Boolean := False; + -- SD I/O enable functions + SDIOEN : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCTRL_Register use record + DTEN at 0 range 0 .. 0; + DTDIR at 0 range 1 .. 1; + DTMODE at 0 range 2 .. 2; + DMAEN at 0 range 3 .. 3; + DBLOCKSIZE at 0 range 4 .. 7; + RWSTART at 0 range 8 .. 8; + RWSTOP at 0 range 9 .. 9; + RWMOD at 0 range 10 .. 10; + SDIOEN at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DCOUNT_DATACOUNT_Field is HAL.UInt25; + + -- data counter register + type DCOUNT_Register is record + -- Read-only. Data count value + DATACOUNT : DCOUNT_DATACOUNT_Field; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCOUNT_Register use record + DATACOUNT at 0 range 0 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- status register + type STA_Register is record + -- Read-only. Command response received (CRC check failed) + CCRCFAIL : Boolean; + -- Read-only. Data block sent/received (CRC check failed) + DCRCFAIL : Boolean; + -- Read-only. Command response timeout + CTIMEOUT : Boolean; + -- Read-only. Data timeout + DTIMEOUT : Boolean; + -- Read-only. Transmit FIFO underrun error + TXUNDERR : Boolean; + -- Read-only. Received FIFO overrun error + RXOVERR : Boolean; + -- Read-only. Command response received (CRC check passed) + CMDREND : Boolean; + -- Read-only. Command sent (no response required) + CMDSENT : Boolean; + -- Read-only. Data end (data counter, SDIDCOUNT, is zero) + DATAEND : Boolean; + -- Read-only. Start bit not detected on all data signals in wide bus + -- mode + STBITERR : Boolean; + -- Read-only. Data block sent/received (CRC check passed) + DBCKEND : Boolean; + -- Read-only. Command transfer in progress + CMDACT : Boolean; + -- Read-only. Data transmit in progress + TXACT : Boolean; + -- Read-only. Data receive in progress + RXACT : Boolean; + -- Read-only. Transmit FIFO half empty: at least 8 words can be written + -- into the FIFO + TXFIFOHE : Boolean; + -- Read-only. Receive FIFO half full: there are at least 8 words in the + -- FIFO + RXFIFOHF : Boolean; + -- Read-only. Transmit FIFO full + TXFIFOF : Boolean; + -- Read-only. Receive FIFO full + RXFIFOF : Boolean; + -- Read-only. Transmit FIFO empty + TXFIFOE : Boolean; + -- Read-only. Receive FIFO empty + RXFIFOE : Boolean; + -- Read-only. Data available in transmit FIFO + TXDAVL : Boolean; + -- Read-only. Data available in receive FIFO + RXDAVL : Boolean; + -- Read-only. SDIO interrupt received + SDIOIT : Boolean; + -- Read-only. CE-ATA command completion signal received for CMD61 + CEATAEND : Boolean; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STA_Register use record + CCRCFAIL at 0 range 0 .. 0; + DCRCFAIL at 0 range 1 .. 1; + CTIMEOUT at 0 range 2 .. 2; + DTIMEOUT at 0 range 3 .. 3; + TXUNDERR at 0 range 4 .. 4; + RXOVERR at 0 range 5 .. 5; + CMDREND at 0 range 6 .. 6; + CMDSENT at 0 range 7 .. 7; + DATAEND at 0 range 8 .. 8; + STBITERR at 0 range 9 .. 9; + DBCKEND at 0 range 10 .. 10; + CMDACT at 0 range 11 .. 11; + TXACT at 0 range 12 .. 12; + RXACT at 0 range 13 .. 13; + TXFIFOHE at 0 range 14 .. 14; + RXFIFOHF at 0 range 15 .. 15; + TXFIFOF at 0 range 16 .. 16; + RXFIFOF at 0 range 17 .. 17; + TXFIFOE at 0 range 18 .. 18; + RXFIFOE at 0 range 19 .. 19; + TXDAVL at 0 range 20 .. 20; + RXDAVL at 0 range 21 .. 21; + SDIOIT at 0 range 22 .. 22; + CEATAEND at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- interrupt clear register + type ICR_Register is record + -- CCRCFAIL flag clear bit + CCRCFAILC : Boolean := False; + -- DCRCFAIL flag clear bit + DCRCFAILC : Boolean := False; + -- CTIMEOUT flag clear bit + CTIMEOUTC : Boolean := False; + -- DTIMEOUT flag clear bit + DTIMEOUTC : Boolean := False; + -- TXUNDERR flag clear bit + TXUNDERRC : Boolean := False; + -- RXOVERR flag clear bit + RXOVERRC : Boolean := False; + -- CMDREND flag clear bit + CMDRENDC : Boolean := False; + -- CMDSENT flag clear bit + CMDSENTC : Boolean := False; + -- DATAEND flag clear bit + DATAENDC : Boolean := False; + -- STBITERR flag clear bit + STBITERRC : Boolean := False; + -- DBCKEND flag clear bit + DBCKENDC : Boolean := False; + -- unspecified + Reserved_11_21 : HAL.UInt11 := 16#0#; + -- SDIOIT flag clear bit + SDIOITC : Boolean := False; + -- CEATAEND flag clear bit + CEATAENDC : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICR_Register use record + CCRCFAILC at 0 range 0 .. 0; + DCRCFAILC at 0 range 1 .. 1; + CTIMEOUTC at 0 range 2 .. 2; + DTIMEOUTC at 0 range 3 .. 3; + TXUNDERRC at 0 range 4 .. 4; + RXOVERRC at 0 range 5 .. 5; + CMDRENDC at 0 range 6 .. 6; + CMDSENTC at 0 range 7 .. 7; + DATAENDC at 0 range 8 .. 8; + STBITERRC at 0 range 9 .. 9; + DBCKENDC at 0 range 10 .. 10; + Reserved_11_21 at 0 range 11 .. 21; + SDIOITC at 0 range 22 .. 22; + CEATAENDC at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- mask register + type MASK_Register is record + -- Command CRC fail interrupt enable + CCRCFAILIE : Boolean := False; + -- Data CRC fail interrupt enable + DCRCFAILIE : Boolean := False; + -- Command timeout interrupt enable + CTIMEOUTIE : Boolean := False; + -- Data timeout interrupt enable + DTIMEOUTIE : Boolean := False; + -- Tx FIFO underrun error interrupt enable + TXUNDERRIE : Boolean := False; + -- Rx FIFO overrun error interrupt enable + RXOVERRIE : Boolean := False; + -- Command response received interrupt enable + CMDRENDIE : Boolean := False; + -- Command sent interrupt enable + CMDSENTIE : Boolean := False; + -- Data end interrupt enable + DATAENDIE : Boolean := False; + -- Start bit error interrupt enable + STBITERRIE : Boolean := False; + -- Data block end interrupt enable + DBCKENDIE : Boolean := False; + -- Command acting interrupt enable + CMDACTIE : Boolean := False; + -- Data transmit acting interrupt enable + TXACTIE : Boolean := False; + -- Data receive acting interrupt enable + RXACTIE : Boolean := False; + -- Tx FIFO half empty interrupt enable + TXFIFOHEIE : Boolean := False; + -- Rx FIFO half full interrupt enable + RXFIFOHFIE : Boolean := False; + -- Tx FIFO full interrupt enable + TXFIFOFIE : Boolean := False; + -- Rx FIFO full interrupt enable + RXFIFOFIE : Boolean := False; + -- Tx FIFO empty interrupt enable + TXFIFOEIE : Boolean := False; + -- Rx FIFO empty interrupt enable + RXFIFOEIE : Boolean := False; + -- Data available in Tx FIFO interrupt enable + TXDAVLIE : Boolean := False; + -- Data available in Rx FIFO interrupt enable + RXDAVLIE : Boolean := False; + -- SDIO mode interrupt received interrupt enable + SDIOITIE : Boolean := False; + -- CE-ATA command completion signal received interrupt enable + CEATAENDIE : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MASK_Register use record + CCRCFAILIE at 0 range 0 .. 0; + DCRCFAILIE at 0 range 1 .. 1; + CTIMEOUTIE at 0 range 2 .. 2; + DTIMEOUTIE at 0 range 3 .. 3; + TXUNDERRIE at 0 range 4 .. 4; + RXOVERRIE at 0 range 5 .. 5; + CMDRENDIE at 0 range 6 .. 6; + CMDSENTIE at 0 range 7 .. 7; + DATAENDIE at 0 range 8 .. 8; + STBITERRIE at 0 range 9 .. 9; + DBCKENDIE at 0 range 10 .. 10; + CMDACTIE at 0 range 11 .. 11; + TXACTIE at 0 range 12 .. 12; + RXACTIE at 0 range 13 .. 13; + TXFIFOHEIE at 0 range 14 .. 14; + RXFIFOHFIE at 0 range 15 .. 15; + TXFIFOFIE at 0 range 16 .. 16; + RXFIFOFIE at 0 range 17 .. 17; + TXFIFOEIE at 0 range 18 .. 18; + RXFIFOEIE at 0 range 19 .. 19; + TXDAVLIE at 0 range 20 .. 20; + RXDAVLIE at 0 range 21 .. 21; + SDIOITIE at 0 range 22 .. 22; + CEATAENDIE at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype FIFOCNT_FIFOCOUNT_Field is HAL.UInt24; + + -- FIFO counter register + type FIFOCNT_Register is record + -- Read-only. Remaining number of words to be written to or read from + -- the FIFO. + FIFOCOUNT : FIFOCNT_FIFOCOUNT_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIFOCNT_Register use record + FIFOCOUNT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Secure digital input/output interface + type SDIO_Peripheral is record + -- power control register + POWER : aliased POWER_Register; + -- SDI clock control register + CLKCR : aliased CLKCR_Register; + -- argument register + ARG : aliased HAL.UInt32; + -- command register + CMD : aliased CMD_Register; + -- command response register + RESPCMD : aliased RESPCMD_Register; + -- response 1..4 register + RESP1 : aliased HAL.UInt32; + -- response 1..4 register + RESP2 : aliased HAL.UInt32; + -- response 1..4 register + RESP3 : aliased HAL.UInt32; + -- response 1..4 register + RESP4 : aliased HAL.UInt32; + -- data timer register + DTIMER : aliased HAL.UInt32; + -- data length register + DLEN : aliased DLEN_Register; + -- data control register + DCTRL : aliased DCTRL_Register; + -- data counter register + DCOUNT : aliased DCOUNT_Register; + -- status register + STA : aliased STA_Register; + -- interrupt clear register + ICR : aliased ICR_Register; + -- mask register + MASK : aliased MASK_Register; + -- FIFO counter register + FIFOCNT : aliased FIFOCNT_Register; + -- data FIFO register + FIFO : aliased HAL.UInt32; + end record + with Volatile; + + for SDIO_Peripheral use record + POWER at 16#0# range 0 .. 31; + CLKCR at 16#4# range 0 .. 31; + ARG at 16#8# range 0 .. 31; + CMD at 16#C# range 0 .. 31; + RESPCMD at 16#10# range 0 .. 31; + RESP1 at 16#14# range 0 .. 31; + RESP2 at 16#18# range 0 .. 31; + RESP3 at 16#1C# range 0 .. 31; + RESP4 at 16#20# range 0 .. 31; + DTIMER at 16#24# range 0 .. 31; + DLEN at 16#28# range 0 .. 31; + DCTRL at 16#2C# range 0 .. 31; + DCOUNT at 16#30# range 0 .. 31; + STA at 16#34# range 0 .. 31; + ICR at 16#38# range 0 .. 31; + MASK at 16#3C# range 0 .. 31; + FIFOCNT at 16#48# range 0 .. 31; + FIFO at 16#80# range 0 .. 31; + end record; + + -- Secure digital input/output interface + SDIO_Periph : aliased SDIO_Peripheral + with Import, Address => SDIO_Base; + +end STM32_SVD.SDIO; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-spi.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-spi.ads new file mode 100644 index 000000000..9e6829845 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-spi.ads @@ -0,0 +1,345 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.SPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CR1_BR_Field is HAL.UInt3; + + -- control register 1 + type CR1_Register is record + -- Clock phase + CPHA : Boolean := False; + -- Clock polarity + CPOL : Boolean := False; + -- Master selection + MSTR : Boolean := False; + -- Baud rate control + BR : CR1_BR_Field := 16#0#; + -- SPI enable + SPE : Boolean := False; + -- Frame format + LSBFIRST : Boolean := False; + -- Internal slave select + SSI : Boolean := False; + -- Software slave management + SSM : Boolean := False; + -- Receive only + RXONLY : Boolean := False; + -- Data frame format + DFF : Boolean := False; + -- CRC transfer next + CRCNEXT : Boolean := False; + -- Hardware CRC calculation enable + CRCEN : Boolean := False; + -- Output enable in bidirectional mode + BIDIOE : Boolean := False; + -- Bidirectional data mode enable + BIDIMODE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register use record + CPHA at 0 range 0 .. 0; + CPOL at 0 range 1 .. 1; + MSTR at 0 range 2 .. 2; + BR at 0 range 3 .. 5; + SPE at 0 range 6 .. 6; + LSBFIRST at 0 range 7 .. 7; + SSI at 0 range 8 .. 8; + SSM at 0 range 9 .. 9; + RXONLY at 0 range 10 .. 10; + DFF at 0 range 11 .. 11; + CRCNEXT at 0 range 12 .. 12; + CRCEN at 0 range 13 .. 13; + BIDIOE at 0 range 14 .. 14; + BIDIMODE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- control register 2 + type CR2_Register is record + -- Rx buffer DMA enable + RXDMAEN : Boolean := False; + -- Tx buffer DMA enable + TXDMAEN : Boolean := False; + -- SS output enable + SSOE : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Frame format + FRF : Boolean := False; + -- Error interrupt enable + ERRIE : Boolean := False; + -- RX buffer not empty interrupt enable + RXNEIE : Boolean := False; + -- Tx buffer empty interrupt enable + TXEIE : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register use record + RXDMAEN at 0 range 0 .. 0; + TXDMAEN at 0 range 1 .. 1; + SSOE at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + FRF at 0 range 4 .. 4; + ERRIE at 0 range 5 .. 5; + RXNEIE at 0 range 6 .. 6; + TXEIE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- status register + type SR_Register is record + -- Read-only. Receive buffer not empty + RXNE : Boolean := False; + -- Read-only. Transmit buffer empty + TXE : Boolean := True; + -- Read-only. Channel side + CHSIDE : Boolean := False; + -- Read-only. Underrun flag + UDR : Boolean := False; + -- CRC error flag + CRCERR : Boolean := False; + -- Read-only. Mode fault + MODF : Boolean := False; + -- Read-only. Overrun flag + OVR : Boolean := False; + -- Read-only. Busy flag + BSY : Boolean := False; + -- Read-only. TI frame format error + TIFRFE : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + RXNE at 0 range 0 .. 0; + TXE at 0 range 1 .. 1; + CHSIDE at 0 range 2 .. 2; + UDR at 0 range 3 .. 3; + CRCERR at 0 range 4 .. 4; + MODF at 0 range 5 .. 5; + OVR at 0 range 6 .. 6; + BSY at 0 range 7 .. 7; + TIFRFE at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype DR_DR_Field is HAL.UInt16; + + -- data register + type DR_Register is record + -- Data register + DR : DR_DR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DR_Register use record + DR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CRCPR_CRCPOLY_Field is HAL.UInt16; + + -- CRC polynomial register + type CRCPR_Register is record + -- CRC polynomial register + CRCPOLY : CRCPR_CRCPOLY_Field := 16#7#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRCPR_Register use record + CRCPOLY at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RXCRCR_RxCRC_Field is HAL.UInt16; + + -- RX CRC register + type RXCRCR_Register is record + -- Read-only. Rx CRC register + RxCRC : RXCRCR_RxCRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXCRCR_Register use record + RxCRC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TXCRCR_TxCRC_Field is HAL.UInt16; + + -- TX CRC register + type TXCRCR_Register is record + -- Read-only. Tx CRC register + TxCRC : TXCRCR_TxCRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXCRCR_Register use record + TxCRC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype I2SCFGR_DATLEN_Field is HAL.UInt2; + subtype I2SCFGR_I2SSTD_Field is HAL.UInt2; + subtype I2SCFGR_I2SCFG_Field is HAL.UInt2; + + -- I2S configuration register + type I2SCFGR_Register is record + -- Channel length (number of bits per audio channel) + CHLEN : Boolean := False; + -- Data length to be transferred + DATLEN : I2SCFGR_DATLEN_Field := 16#0#; + -- Steady state clock polarity + CKPOL : Boolean := False; + -- I2S standard selection + I2SSTD : I2SCFGR_I2SSTD_Field := 16#0#; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- PCM frame synchronization + PCMSYNC : Boolean := False; + -- I2S configuration mode + I2SCFG : I2SCFGR_I2SCFG_Field := 16#0#; + -- I2S Enable + I2SE : Boolean := False; + -- I2S mode selection + I2SMOD : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for I2SCFGR_Register use record + CHLEN at 0 range 0 .. 0; + DATLEN at 0 range 1 .. 2; + CKPOL at 0 range 3 .. 3; + I2SSTD at 0 range 4 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PCMSYNC at 0 range 7 .. 7; + I2SCFG at 0 range 8 .. 9; + I2SE at 0 range 10 .. 10; + I2SMOD at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype I2SPR_I2SDIV_Field is HAL.UInt8; + + -- I2S prescaler register + type I2SPR_Register is record + -- I2S Linear prescaler + I2SDIV : I2SPR_I2SDIV_Field := 16#A#; + -- Odd factor for the prescaler + ODD : Boolean := False; + -- Master clock output enable + MCKOE : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for I2SPR_Register use record + I2SDIV at 0 range 0 .. 7; + ODD at 0 range 8 .. 8; + MCKOE at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Serial peripheral interface + type SPI_Peripheral is record + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register; + -- status register + SR : aliased SR_Register; + -- data register + DR : aliased DR_Register; + -- CRC polynomial register + CRCPR : aliased CRCPR_Register; + -- RX CRC register + RXCRCR : aliased RXCRCR_Register; + -- TX CRC register + TXCRCR : aliased TXCRCR_Register; + -- I2S configuration register + I2SCFGR : aliased I2SCFGR_Register; + -- I2S prescaler register + I2SPR : aliased I2SPR_Register; + end record + with Volatile; + + for SPI_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; + DR at 16#C# range 0 .. 31; + CRCPR at 16#10# range 0 .. 31; + RXCRCR at 16#14# range 0 .. 31; + TXCRCR at 16#18# range 0 .. 31; + I2SCFGR at 16#1C# range 0 .. 31; + I2SPR at 16#20# range 0 .. 31; + end record; + + -- Serial peripheral interface + I2S2ext_Periph : aliased SPI_Peripheral + with Import, Address => I2S2ext_Base; + + -- Serial peripheral interface + I2S3ext_Periph : aliased SPI_Peripheral + with Import, Address => I2S3ext_Base; + + -- Serial peripheral interface + SPI1_Periph : aliased SPI_Peripheral + with Import, Address => SPI1_Base; + + -- Serial peripheral interface + SPI2_Periph : aliased SPI_Peripheral + with Import, Address => SPI2_Base; + + -- Serial peripheral interface + SPI3_Periph : aliased SPI_Peripheral + with Import, Address => SPI3_Base; + + -- Serial peripheral interface + SPI4_Periph : aliased SPI_Peripheral + with Import, Address => SPI4_Base; + +end STM32_SVD.SPI; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-stk.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-stk.ads new file mode 100644 index 000000000..fbc2955f1 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-stk.ads @@ -0,0 +1,129 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.STK is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- SysTick control and status register + type CTRL_Register is record + -- Counter enable + ENABLE : Boolean := False; + -- SysTick exception request enable + TICKINT : Boolean := False; + -- Clock source selection + CLKSOURCE : Boolean := False; + -- unspecified + Reserved_3_15 : HAL.UInt13 := 16#0#; + -- COUNTFLAG + COUNTFLAG : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + ENABLE at 0 range 0 .. 0; + TICKINT at 0 range 1 .. 1; + CLKSOURCE at 0 range 2 .. 2; + Reserved_3_15 at 0 range 3 .. 15; + COUNTFLAG at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype LOAD_RELOAD_Field is HAL.UInt24; + + -- SysTick reload value register + type LOAD_Register is record + -- RELOAD value + RELOAD : LOAD_RELOAD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOAD_Register use record + RELOAD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype VAL_CURRENT_Field is HAL.UInt24; + + -- SysTick current value register + type VAL_Register is record + -- Current counter value + CURRENT : VAL_CURRENT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VAL_Register use record + CURRENT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CALIB_TENMS_Field is HAL.UInt24; + + -- SysTick calibration value register + type CALIB_Register is record + -- Calibration value + TENMS : CALIB_TENMS_Field := 16#0#; + -- unspecified + Reserved_24_29 : HAL.UInt6 := 16#0#; + -- SKEW flag: Indicates whether the TENMS value is exact + SKEW : Boolean := False; + -- NOREF flag. Reads as zero + NOREF : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CALIB_Register use record + TENMS at 0 range 0 .. 23; + Reserved_24_29 at 0 range 24 .. 29; + SKEW at 0 range 30 .. 30; + NOREF at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- SysTick timer + type STK_Peripheral is record + -- SysTick control and status register + CTRL : aliased CTRL_Register; + -- SysTick reload value register + LOAD : aliased LOAD_Register; + -- SysTick current value register + VAL : aliased VAL_Register; + -- SysTick calibration value register + CALIB : aliased CALIB_Register; + end record + with Volatile; + + for STK_Peripheral use record + CTRL at 16#0# range 0 .. 31; + LOAD at 16#4# range 0 .. 31; + VAL at 16#8# range 0 .. 31; + CALIB at 16#C# range 0 .. 31; + end record; + + -- SysTick timer + STK_Periph : aliased STK_Peripheral + with Import, Address => STK_Base; + +end STM32_SVD.STK; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-syscfg.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-syscfg.ads new file mode 100644 index 000000000..e584ef584 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-syscfg.ads @@ -0,0 +1,282 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.SYSCFG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype MEMRM_MEM_MODE_Field is HAL.UInt2; + + -- memory remap register + type MEMRM_Register is record + -- MEM_MODE + MEM_MODE : MEMRM_MEM_MODE_Field := 16#0#; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MEMRM_Register use record + MEM_MODE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- peripheral mode configuration register + type PMC_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- ADC1DC2 + ADC1DC2 : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_Register use record + Reserved_0_15 at 0 range 0 .. 15; + ADC1DC2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- EXTICR1_EXTI array element + subtype EXTICR1_EXTI_Element is HAL.UInt4; + + -- EXTICR1_EXTI array + type EXTICR1_EXTI_Field_Array is array (0 .. 3) of EXTICR1_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR1_EXTI + type EXTICR1_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : HAL.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR1_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR1_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 1 + type EXTICR1_Register is record + -- EXTI x configuration (x = 0 to 3) + EXTI : EXTICR1_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTICR1_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR2_EXTI array element + subtype EXTICR2_EXTI_Element is HAL.UInt4; + + -- EXTICR2_EXTI array + type EXTICR2_EXTI_Field_Array is array (4 .. 7) of EXTICR2_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR2_EXTI + type EXTICR2_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : HAL.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR2_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR2_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 2 + type EXTICR2_Register is record + -- EXTI x configuration (x = 4 to 7) + EXTI : EXTICR2_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTICR2_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR3_EXTI array element + subtype EXTICR3_EXTI_Element is HAL.UInt4; + + -- EXTICR3_EXTI array + type EXTICR3_EXTI_Field_Array is array (8 .. 11) of EXTICR3_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR3_EXTI + type EXTICR3_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : HAL.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR3_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR3_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 3 + type EXTICR3_Register is record + -- EXTI x configuration (x = 8 to 11) + EXTI : EXTICR3_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTICR3_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR4_EXTI array element + subtype EXTICR4_EXTI_Element is HAL.UInt4; + + -- EXTICR4_EXTI array + type EXTICR4_EXTI_Field_Array is array (12 .. 15) of EXTICR4_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR4_EXTI + type EXTICR4_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : HAL.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR4_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR4_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 4 + type EXTICR4_Register is record + -- EXTI x configuration (x = 12 to 15) + EXTI : EXTICR4_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTICR4_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Compensation cell control register + type CMPCR_Register is record + -- Read-only. Compensation cell power-down + CMP_PD : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. READY + READY : Boolean; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CMPCR_Register use record + CMP_PD at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + READY at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- System configuration controller + type SYSCFG_Peripheral is record + -- memory remap register + MEMRM : aliased MEMRM_Register; + -- peripheral mode configuration register + PMC : aliased PMC_Register; + -- external interrupt configuration register 1 + EXTICR1 : aliased EXTICR1_Register; + -- external interrupt configuration register 2 + EXTICR2 : aliased EXTICR2_Register; + -- external interrupt configuration register 3 + EXTICR3 : aliased EXTICR3_Register; + -- external interrupt configuration register 4 + EXTICR4 : aliased EXTICR4_Register; + -- Compensation cell control register + CMPCR : aliased CMPCR_Register; + end record + with Volatile; + + for SYSCFG_Peripheral use record + MEMRM at 16#0# range 0 .. 31; + PMC at 16#4# range 0 .. 31; + EXTICR1 at 16#8# range 0 .. 31; + EXTICR2 at 16#C# range 0 .. 31; + EXTICR3 at 16#10# range 0 .. 31; + EXTICR4 at 16#14# range 0 .. 31; + CMPCR at 16#20# range 0 .. 31; + end record; + + -- System configuration controller + SYSCFG_Periph : aliased SYSCFG_Peripheral + with Import, Address => SYSCFG_Base; + +end STM32_SVD.SYSCFG; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-tim.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-tim.ads new file mode 100644 index 000000000..44ad4a852 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-tim.ads @@ -0,0 +1,2125 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.TIM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CR1_CMS_Field is HAL.UInt2; + subtype CR1_CKD_Field is HAL.UInt2; + + -- control register 1 + type CR1_Register is record + -- Counter enable + CEN : Boolean := False; + -- Update disable + UDIS : Boolean := False; + -- Update request source + URS : Boolean := False; + -- One-pulse mode + OPM : Boolean := False; + -- Direction + DIR : Boolean := False; + -- Center-aligned mode selection + CMS : CR1_CMS_Field := 16#0#; + -- Auto-reload preload enable + ARPE : Boolean := False; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + DIR at 0 range 4 .. 4; + CMS at 0 range 5 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype CR2_MMS_Field is HAL.UInt3; + + -- control register 2 + type CR2_Register is record + -- Capture/compare preloaded control + CCPC : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Capture/compare control update selection + CCUS : Boolean := False; + -- Capture/compare DMA selection + CCDS : Boolean := False; + -- Master mode selection + MMS : CR2_MMS_Field := 16#0#; + -- TI1 selection + TI1S : Boolean := False; + -- Output Idle state 1 + OIS1 : Boolean := False; + -- Output Idle state 1 + OIS1N : Boolean := False; + -- Output Idle state 2 + OIS2 : Boolean := False; + -- Output Idle state 2 + OIS2N : Boolean := False; + -- Output Idle state 3 + OIS3 : Boolean := False; + -- Output Idle state 3 + OIS3N : Boolean := False; + -- Output Idle state 4 + OIS4 : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register use record + CCPC at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + CCUS at 0 range 2 .. 2; + CCDS at 0 range 3 .. 3; + MMS at 0 range 4 .. 6; + TI1S at 0 range 7 .. 7; + OIS1 at 0 range 8 .. 8; + OIS1N at 0 range 9 .. 9; + OIS2 at 0 range 10 .. 10; + OIS2N at 0 range 11 .. 11; + OIS3 at 0 range 12 .. 12; + OIS3N at 0 range 13 .. 13; + OIS4 at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype SMCR_SMS_Field is HAL.UInt3; + subtype SMCR_TS_Field is HAL.UInt3; + subtype SMCR_ETF_Field is HAL.UInt4; + subtype SMCR_ETPS_Field is HAL.UInt2; + + -- slave mode control register + type SMCR_Register is record + -- Slave mode selection + SMS : SMCR_SMS_Field := 16#0#; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Trigger selection + TS : SMCR_TS_Field := 16#0#; + -- Master/Slave mode + MSM : Boolean := False; + -- External trigger filter + ETF : SMCR_ETF_Field := 16#0#; + -- External trigger prescaler + ETPS : SMCR_ETPS_Field := 16#0#; + -- External clock enable + ECE : Boolean := False; + -- External trigger polarity + ETP : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SMCR_Register use record + SMS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + TS at 0 range 4 .. 6; + MSM at 0 range 7 .. 7; + ETF at 0 range 8 .. 11; + ETPS at 0 range 12 .. 13; + ECE at 0 range 14 .. 14; + ETP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register is record + -- Update interrupt enable + UIE : Boolean := False; + -- Capture/Compare 1 interrupt enable + CC1IE : Boolean := False; + -- Capture/Compare 2 interrupt enable + CC2IE : Boolean := False; + -- Capture/Compare 3 interrupt enable + CC3IE : Boolean := False; + -- Capture/Compare 4 interrupt enable + CC4IE : Boolean := False; + -- COM interrupt enable + COMIE : Boolean := False; + -- Trigger interrupt enable + TIE : Boolean := False; + -- Break interrupt enable + BIE : Boolean := False; + -- Update DMA request enable + UDE : Boolean := False; + -- Capture/Compare 1 DMA request enable + CC1DE : Boolean := False; + -- Capture/Compare 2 DMA request enable + CC2DE : Boolean := False; + -- Capture/Compare 3 DMA request enable + CC3DE : Boolean := False; + -- Capture/Compare 4 DMA request enable + CC4DE : Boolean := False; + -- COM DMA request enable + COMDE : Boolean := False; + -- Trigger DMA request enable + TDE : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIER_Register use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + CC2IE at 0 range 2 .. 2; + CC3IE at 0 range 3 .. 3; + CC4IE at 0 range 4 .. 4; + COMIE at 0 range 5 .. 5; + TIE at 0 range 6 .. 6; + BIE at 0 range 7 .. 7; + UDE at 0 range 8 .. 8; + CC1DE at 0 range 9 .. 9; + CC2DE at 0 range 10 .. 10; + CC3DE at 0 range 11 .. 11; + CC4DE at 0 range 12 .. 12; + COMDE at 0 range 13 .. 13; + TDE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- status register + type SR_Register is record + -- Update interrupt flag + UIF : Boolean := False; + -- Capture/compare 1 interrupt flag + CC1IF : Boolean := False; + -- Capture/Compare 2 interrupt flag + CC2IF : Boolean := False; + -- Capture/Compare 3 interrupt flag + CC3IF : Boolean := False; + -- Capture/Compare 4 interrupt flag + CC4IF : Boolean := False; + -- COM interrupt flag + COMIF : Boolean := False; + -- Trigger interrupt flag + TIF : Boolean := False; + -- Break interrupt flag + BIF : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : Boolean := False; + -- Capture/compare 2 overcapture flag + CC2OF : Boolean := False; + -- Capture/Compare 3 overcapture flag + CC3OF : Boolean := False; + -- Capture/Compare 4 overcapture flag + CC4OF : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + CC2IF at 0 range 2 .. 2; + CC3IF at 0 range 3 .. 3; + CC4IF at 0 range 4 .. 4; + COMIF at 0 range 5 .. 5; + TIF at 0 range 6 .. 6; + BIF at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + CC1OF at 0 range 9 .. 9; + CC2OF at 0 range 10 .. 10; + CC3OF at 0 range 11 .. 11; + CC4OF at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- event generation register + type EGR_Register is record + -- Write-only. Update generation + UG : Boolean := False; + -- Write-only. Capture/compare 1 generation + CC1G : Boolean := False; + -- Write-only. Capture/compare 2 generation + CC2G : Boolean := False; + -- Write-only. Capture/compare 3 generation + CC3G : Boolean := False; + -- Write-only. Capture/compare 4 generation + CC4G : Boolean := False; + -- Write-only. Capture/Compare control update generation + COMG : Boolean := False; + -- Write-only. Trigger generation + TG : Boolean := False; + -- Write-only. Break generation + BG : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EGR_Register use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + CC2G at 0 range 2 .. 2; + CC3G at 0 range 3 .. 3; + CC4G at 0 range 4 .. 4; + COMG at 0 range 5 .. 5; + TG at 0 range 6 .. 6; + BG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CCMR1_Output_CC1S_Field is HAL.UInt2; + subtype CCMR1_Output_OC1M_Field is HAL.UInt3; + subtype CCMR1_Output_CC2S_Field is HAL.UInt2; + subtype CCMR1_Output_OC2M_Field is HAL.UInt3; + + -- capture/compare mode register 1 (output mode) + type CCMR1_Output_Register is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Output_CC1S_Field := 16#0#; + -- Output Compare 1 fast enable + OC1FE : Boolean := False; + -- Output Compare 1 preload enable + OC1PE : Boolean := False; + -- Output Compare 1 mode + OC1M : CCMR1_Output_OC1M_Field := 16#0#; + -- Output Compare 1 clear enable + OC1CE : Boolean := False; + -- Capture/Compare 2 selection + CC2S : CCMR1_Output_CC2S_Field := 16#0#; + -- Output Compare 2 fast enable + OC2FE : Boolean := False; + -- Output Compare 2 preload enable + OC2PE : Boolean := False; + -- Output Compare 2 mode + OC2M : CCMR1_Output_OC2M_Field := 16#0#; + -- Output Compare 2 clear enable + OC2CE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Output_Register use record + CC1S at 0 range 0 .. 1; + OC1FE at 0 range 2 .. 2; + OC1PE at 0 range 3 .. 3; + OC1M at 0 range 4 .. 6; + OC1CE at 0 range 7 .. 7; + CC2S at 0 range 8 .. 9; + OC2FE at 0 range 10 .. 10; + OC2PE at 0 range 11 .. 11; + OC2M at 0 range 12 .. 14; + OC2CE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCMR1_Input_CC1S_Field is HAL.UInt2; + subtype CCMR1_Input_ICPCS_Field is HAL.UInt2; + subtype CCMR1_Input_IC1F_Field is HAL.UInt4; + subtype CCMR1_Input_CC2S_Field is HAL.UInt2; + subtype CCMR1_Input_IC2PCS_Field is HAL.UInt2; + subtype CCMR1_Input_IC2F_Field is HAL.UInt4; + + -- capture/compare mode register 1 (input mode) + type CCMR1_Input_Register is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Input_CC1S_Field := 16#0#; + -- Input capture 1 prescaler + ICPCS : CCMR1_Input_ICPCS_Field := 16#0#; + -- Input capture 1 filter + IC1F : CCMR1_Input_IC1F_Field := 16#0#; + -- Capture/Compare 2 selection + CC2S : CCMR1_Input_CC2S_Field := 16#0#; + -- Input capture 2 prescaler + IC2PCS : CCMR1_Input_IC2PCS_Field := 16#0#; + -- Input capture 2 filter + IC2F : CCMR1_Input_IC2F_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Input_Register use record + CC1S at 0 range 0 .. 1; + ICPCS at 0 range 2 .. 3; + IC1F at 0 range 4 .. 7; + CC2S at 0 range 8 .. 9; + IC2PCS at 0 range 10 .. 11; + IC2F at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCMR2_Output_CC3S_Field is HAL.UInt2; + subtype CCMR2_Output_OC3M_Field is HAL.UInt3; + subtype CCMR2_Output_CC4S_Field is HAL.UInt2; + subtype CCMR2_Output_OC4M_Field is HAL.UInt3; + + -- capture/compare mode register 2 (output mode) + type CCMR2_Output_Register is record + -- Capture/Compare 3 selection + CC3S : CCMR2_Output_CC3S_Field := 16#0#; + -- Output compare 3 fast enable + OC3FE : Boolean := False; + -- Output compare 3 preload enable + OC3PE : Boolean := False; + -- Output compare 3 mode + OC3M : CCMR2_Output_OC3M_Field := 16#0#; + -- Output compare 3 clear enable + OC3CE : Boolean := False; + -- Capture/Compare 4 selection + CC4S : CCMR2_Output_CC4S_Field := 16#0#; + -- Output compare 4 fast enable + OC4FE : Boolean := False; + -- Output compare 4 preload enable + OC4PE : Boolean := False; + -- Output compare 4 mode + OC4M : CCMR2_Output_OC4M_Field := 16#0#; + -- Output compare 4 clear enable + OC4CE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR2_Output_Register use record + CC3S at 0 range 0 .. 1; + OC3FE at 0 range 2 .. 2; + OC3PE at 0 range 3 .. 3; + OC3M at 0 range 4 .. 6; + OC3CE at 0 range 7 .. 7; + CC4S at 0 range 8 .. 9; + OC4FE at 0 range 10 .. 10; + OC4PE at 0 range 11 .. 11; + OC4M at 0 range 12 .. 14; + OC4CE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCMR2_Input_CC3S_Field is HAL.UInt2; + subtype CCMR2_Input_IC3PSC_Field is HAL.UInt2; + subtype CCMR2_Input_IC3F_Field is HAL.UInt4; + subtype CCMR2_Input_CC4S_Field is HAL.UInt2; + subtype CCMR2_Input_IC4PSC_Field is HAL.UInt2; + subtype CCMR2_Input_IC4F_Field is HAL.UInt4; + + -- capture/compare mode register 2 (input mode) + type CCMR2_Input_Register is record + -- Capture/compare 3 selection + CC3S : CCMR2_Input_CC3S_Field := 16#0#; + -- Input capture 3 prescaler + IC3PSC : CCMR2_Input_IC3PSC_Field := 16#0#; + -- Input capture 3 filter + IC3F : CCMR2_Input_IC3F_Field := 16#0#; + -- Capture/Compare 4 selection + CC4S : CCMR2_Input_CC4S_Field := 16#0#; + -- Input capture 4 prescaler + IC4PSC : CCMR2_Input_IC4PSC_Field := 16#0#; + -- Input capture 4 filter + IC4F : CCMR2_Input_IC4F_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR2_Input_Register use record + CC3S at 0 range 0 .. 1; + IC3PSC at 0 range 2 .. 3; + IC3F at 0 range 4 .. 7; + CC4S at 0 range 8 .. 9; + IC4PSC at 0 range 10 .. 11; + IC4F at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register is record + -- Capture/Compare 1 output enable + CC1E : Boolean := False; + -- Capture/Compare 1 output Polarity + CC1P : Boolean := False; + -- Capture/Compare 1 complementary output enable + CC1NE : Boolean := False; + -- Capture/Compare 1 output Polarity + CC1NP : Boolean := False; + -- Capture/Compare 2 output enable + CC2E : Boolean := False; + -- Capture/Compare 2 output Polarity + CC2P : Boolean := False; + -- Capture/Compare 2 complementary output enable + CC2NE : Boolean := False; + -- Capture/Compare 2 output Polarity + CC2NP : Boolean := False; + -- Capture/Compare 3 output enable + CC3E : Boolean := False; + -- Capture/Compare 3 output Polarity + CC3P : Boolean := False; + -- Capture/Compare 3 complementary output enable + CC3NE : Boolean := False; + -- Capture/Compare 3 output Polarity + CC3NP : Boolean := False; + -- Capture/Compare 4 output enable + CC4E : Boolean := False; + -- Capture/Compare 3 output Polarity + CC4P : Boolean := False; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCER_Register use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + CC1NE at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + CC2E at 0 range 4 .. 4; + CC2P at 0 range 5 .. 5; + CC2NE at 0 range 6 .. 6; + CC2NP at 0 range 7 .. 7; + CC3E at 0 range 8 .. 8; + CC3P at 0 range 9 .. 9; + CC3NE at 0 range 10 .. 10; + CC3NP at 0 range 11 .. 11; + CC4E at 0 range 12 .. 12; + CC4P at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype CNT_CNT_Field is HAL.UInt16; + + -- counter + type CNT_Register is record + -- counter value + CNT : CNT_CNT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CNT_Register use record + CNT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype PSC_PSC_Field is HAL.UInt16; + + -- prescaler + type PSC_Register is record + -- Prescaler value + PSC : PSC_PSC_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSC_Register use record + PSC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ARR_ARR_Field is HAL.UInt16; + + -- auto-reload register + type ARR_Register is record + -- Auto-reload value + ARR : ARR_ARR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARR_Register use record + ARR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RCR_REP_Field is HAL.UInt8; + + -- repetition counter register + type RCR_Register is record + -- Repetition counter value + REP : RCR_REP_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RCR_Register use record + REP at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CCR1_CCR1_Field is HAL.UInt16; + + -- capture/compare register 1 + type CCR1_Register is record + -- Capture/Compare 1 value + CCR1 : CCR1_CCR1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR1_Register use record + CCR1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR2_CCR2_Field is HAL.UInt16; + + -- capture/compare register 2 + type CCR2_Register is record + -- Capture/Compare 2 value + CCR2 : CCR2_CCR2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR2_Register use record + CCR2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_Field is HAL.UInt16; + + -- capture/compare register 3 + type CCR3_Register is record + -- Capture/Compare value + CCR3 : CCR3_CCR3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR3_Register use record + CCR3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_Field is HAL.UInt16; + + -- capture/compare register 4 + type CCR4_Register is record + -- Capture/Compare value + CCR4 : CCR4_CCR4_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR4_Register use record + CCR4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BDTR_DTG_Field is HAL.UInt8; + subtype BDTR_LOCK_Field is HAL.UInt2; + + -- break and dead-time register + type BDTR_Register is record + -- Dead-time generator setup + DTG : BDTR_DTG_Field := 16#0#; + -- Lock configuration + LOCK : BDTR_LOCK_Field := 16#0#; + -- Off-state selection for Idle mode + OSSI : Boolean := False; + -- Off-state selection for Run mode + OSSR : Boolean := False; + -- Break enable + BKE : Boolean := False; + -- Break polarity + BKP : Boolean := False; + -- Automatic output enable + AOE : Boolean := False; + -- Main output enable + MOE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BDTR_Register use record + DTG at 0 range 0 .. 7; + LOCK at 0 range 8 .. 9; + OSSI at 0 range 10 .. 10; + OSSR at 0 range 11 .. 11; + BKE at 0 range 12 .. 12; + BKP at 0 range 13 .. 13; + AOE at 0 range 14 .. 14; + MOE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DCR_DBA_Field is HAL.UInt5; + subtype DCR_DBL_Field is HAL.UInt5; + + -- DMA control register + type DCR_Register is record + -- DMA base address + DBA : DCR_DBA_Field := 16#0#; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- DMA burst length + DBL : DCR_DBL_Field := 16#0#; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCR_Register use record + DBA at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + DBL at 0 range 8 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype DMAR_DMAB_Field is HAL.UInt16; + + -- DMA address for full transfer + type DMAR_Register is record + -- DMA register for burst accesses + DMAB : DMAR_DMAB_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DMAR_Register use record + DMAB at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- control register 2 + type CR2_Register_1 is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Capture/compare DMA selection + CCDS : Boolean := False; + -- Master mode selection + MMS : CR2_MMS_Field := 16#0#; + -- TI1 selection + TI1S : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register_1 use record + Reserved_0_2 at 0 range 0 .. 2; + CCDS at 0 range 3 .. 3; + MMS at 0 range 4 .. 6; + TI1S at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_1 is record + -- Update interrupt enable + UIE : Boolean := False; + -- Capture/Compare 1 interrupt enable + CC1IE : Boolean := False; + -- Capture/Compare 2 interrupt enable + CC2IE : Boolean := False; + -- Capture/Compare 3 interrupt enable + CC3IE : Boolean := False; + -- Capture/Compare 4 interrupt enable + CC4IE : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Trigger interrupt enable + TIE : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Update DMA request enable + UDE : Boolean := False; + -- Capture/Compare 1 DMA request enable + CC1DE : Boolean := False; + -- Capture/Compare 2 DMA request enable + CC2DE : Boolean := False; + -- Capture/Compare 3 DMA request enable + CC3DE : Boolean := False; + -- Capture/Compare 4 DMA request enable + CC4DE : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Trigger DMA request enable + TDE : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIER_Register_1 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + CC2IE at 0 range 2 .. 2; + CC3IE at 0 range 3 .. 3; + CC4IE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TIE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + UDE at 0 range 8 .. 8; + CC1DE at 0 range 9 .. 9; + CC2DE at 0 range 10 .. 10; + CC3DE at 0 range 11 .. 11; + CC4DE at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + TDE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- status register + type SR_Register_1 is record + -- Update interrupt flag + UIF : Boolean := False; + -- Capture/compare 1 interrupt flag + CC1IF : Boolean := False; + -- Capture/Compare 2 interrupt flag + CC2IF : Boolean := False; + -- Capture/Compare 3 interrupt flag + CC3IF : Boolean := False; + -- Capture/Compare 4 interrupt flag + CC4IF : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Trigger interrupt flag + TIF : Boolean := False; + -- unspecified + Reserved_7_8 : HAL.UInt2 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : Boolean := False; + -- Capture/compare 2 overcapture flag + CC2OF : Boolean := False; + -- Capture/Compare 3 overcapture flag + CC3OF : Boolean := False; + -- Capture/Compare 4 overcapture flag + CC4OF : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register_1 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + CC2IF at 0 range 2 .. 2; + CC3IF at 0 range 3 .. 3; + CC4IF at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TIF at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + CC1OF at 0 range 9 .. 9; + CC2OF at 0 range 10 .. 10; + CC3OF at 0 range 11 .. 11; + CC4OF at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- event generation register + type EGR_Register_1 is record + -- Write-only. Update generation + UG : Boolean := False; + -- Write-only. Capture/compare 1 generation + CC1G : Boolean := False; + -- Write-only. Capture/compare 2 generation + CC2G : Boolean := False; + -- Write-only. Capture/compare 3 generation + CC3G : Boolean := False; + -- Write-only. Capture/compare 4 generation + CC4G : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Write-only. Trigger generation + TG : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EGR_Register_1 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + CC2G at 0 range 2 .. 2; + CC3G at 0 range 3 .. 3; + CC4G at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TG at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- capture/compare mode register 2 (output mode) + type CCMR2_Output_Register_1 is record + -- CC3S + CC3S : CCMR2_Output_CC3S_Field := 16#0#; + -- OC3FE + OC3FE : Boolean := False; + -- OC3PE + OC3PE : Boolean := False; + -- OC3M + OC3M : CCMR2_Output_OC3M_Field := 16#0#; + -- OC3CE + OC3CE : Boolean := False; + -- CC4S + CC4S : CCMR2_Output_CC4S_Field := 16#0#; + -- OC4FE + OC4FE : Boolean := False; + -- OC4PE + OC4PE : Boolean := False; + -- OC4M + OC4M : CCMR2_Output_OC4M_Field := 16#0#; + -- O24CE + O24CE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR2_Output_Register_1 use record + CC3S at 0 range 0 .. 1; + OC3FE at 0 range 2 .. 2; + OC3PE at 0 range 3 .. 3; + OC3M at 0 range 4 .. 6; + OC3CE at 0 range 7 .. 7; + CC4S at 0 range 8 .. 9; + OC4FE at 0 range 10 .. 10; + OC4PE at 0 range 11 .. 11; + OC4M at 0 range 12 .. 14; + O24CE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register_1 is record + -- Capture/Compare 1 output enable + CC1E : Boolean := False; + -- Capture/Compare 1 output Polarity + CC1P : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : Boolean := False; + -- Capture/Compare 2 output enable + CC2E : Boolean := False; + -- Capture/Compare 2 output Polarity + CC2P : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Capture/Compare 2 output Polarity + CC2NP : Boolean := False; + -- Capture/Compare 3 output enable + CC3E : Boolean := False; + -- Capture/Compare 3 output Polarity + CC3P : Boolean := False; + -- unspecified + Reserved_10_10 : HAL.Bit := 16#0#; + -- Capture/Compare 3 output Polarity + CC3NP : Boolean := False; + -- Capture/Compare 4 output enable + CC4E : Boolean := False; + -- Capture/Compare 3 output Polarity + CC4P : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Capture/Compare 4 output Polarity + CC4NP : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCER_Register_1 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + CC2E at 0 range 4 .. 4; + CC2P at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + CC2NP at 0 range 7 .. 7; + CC3E at 0 range 8 .. 8; + CC3P at 0 range 9 .. 9; + Reserved_10_10 at 0 range 10 .. 10; + CC3NP at 0 range 11 .. 11; + CC4E at 0 range 12 .. 12; + CC4P at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + CC4NP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CNT_CNT_L_Field is HAL.UInt16; + subtype CNT_CNT_H_Field is HAL.UInt16; + + -- counter + type CNT_Register_1 is record + -- Low counter value + CNT_L : CNT_CNT_L_Field := 16#0#; + -- High counter value + CNT_H : CNT_CNT_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CNT_Register_1 use record + CNT_L at 0 range 0 .. 15; + CNT_H at 0 range 16 .. 31; + end record; + + subtype ARR_ARR_L_Field is HAL.UInt16; + subtype ARR_ARR_H_Field is HAL.UInt16; + + -- auto-reload register + type ARR_Register_1 is record + -- Low Auto-reload value + ARR_L : ARR_ARR_L_Field := 16#0#; + -- High Auto-reload value + ARR_H : ARR_ARR_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARR_Register_1 use record + ARR_L at 0 range 0 .. 15; + ARR_H at 0 range 16 .. 31; + end record; + + subtype CCR1_CCR1_L_Field is HAL.UInt16; + subtype CCR1_CCR1_H_Field is HAL.UInt16; + + -- capture/compare register 1 + type CCR1_Register_1 is record + -- Low Capture/Compare 1 value + CCR1_L : CCR1_CCR1_L_Field := 16#0#; + -- High Capture/Compare 1 value + CCR1_H : CCR1_CCR1_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR1_Register_1 use record + CCR1_L at 0 range 0 .. 15; + CCR1_H at 0 range 16 .. 31; + end record; + + subtype CCR2_CCR2_L_Field is HAL.UInt16; + subtype CCR2_CCR2_H_Field is HAL.UInt16; + + -- capture/compare register 2 + type CCR2_Register_1 is record + -- Low Capture/Compare 2 value + CCR2_L : CCR2_CCR2_L_Field := 16#0#; + -- High Capture/Compare 2 value + CCR2_H : CCR2_CCR2_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR2_Register_1 use record + CCR2_L at 0 range 0 .. 15; + CCR2_H at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_L_Field is HAL.UInt16; + subtype CCR3_CCR3_H_Field is HAL.UInt16; + + -- capture/compare register 3 + type CCR3_Register_1 is record + -- Low Capture/Compare value + CCR3_L : CCR3_CCR3_L_Field := 16#0#; + -- High Capture/Compare value + CCR3_H : CCR3_CCR3_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR3_Register_1 use record + CCR3_L at 0 range 0 .. 15; + CCR3_H at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_L_Field is HAL.UInt16; + subtype CCR4_CCR4_H_Field is HAL.UInt16; + + -- capture/compare register 4 + type CCR4_Register_1 is record + -- Low Capture/Compare value + CCR4_L : CCR4_CCR4_L_Field := 16#0#; + -- High Capture/Compare value + CCR4_H : CCR4_CCR4_H_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR4_Register_1 use record + CCR4_L at 0 range 0 .. 15; + CCR4_H at 0 range 16 .. 31; + end record; + + subtype OR_ITR1_RMP_Field is HAL.UInt2; + + -- TIM5 option register + type OR_Register is record + -- unspecified + Reserved_0_9 : HAL.UInt10 := 16#0#; + -- Timer Input 4 remap + ITR1_RMP : OR_ITR1_RMP_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OR_Register use record + Reserved_0_9 at 0 range 0 .. 9; + ITR1_RMP at 0 range 10 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype OR_IT4_RMP_Field is HAL.UInt2; + + -- TIM5 option register + type OR_Register_1 is record + -- unspecified + Reserved_0_5 : HAL.UInt6 := 16#0#; + -- Timer Input 4 remap + IT4_RMP : OR_IT4_RMP_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OR_Register_1 use record + Reserved_0_5 at 0 range 0 .. 5; + IT4_RMP at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- control register 1 + type CR1_Register_1 is record + -- Counter enable + CEN : Boolean := False; + -- Update disable + UDIS : Boolean := False; + -- Update request source + URS : Boolean := False; + -- One-pulse mode + OPM : Boolean := False; + -- unspecified + Reserved_4_6 : HAL.UInt3 := 16#0#; + -- Auto-reload preload enable + ARPE : Boolean := False; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register_1 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- control register 2 + type CR2_Register_2 is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Master mode selection + MMS : CR2_MMS_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register_2 use record + Reserved_0_3 at 0 range 0 .. 3; + MMS at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- slave mode control register + type SMCR_Register_1 is record + -- Slave mode selection + SMS : SMCR_SMS_Field := 16#0#; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Trigger selection + TS : SMCR_TS_Field := 16#0#; + -- Master/Slave mode + MSM : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SMCR_Register_1 use record + SMS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + TS at 0 range 4 .. 6; + MSM at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_2 is record + -- Update interrupt enable + UIE : Boolean := False; + -- Capture/Compare 1 interrupt enable + CC1IE : Boolean := False; + -- Capture/Compare 2 interrupt enable + CC2IE : Boolean := False; + -- unspecified + Reserved_3_5 : HAL.UInt3 := 16#0#; + -- Trigger interrupt enable + TIE : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIER_Register_2 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + CC2IE at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TIE at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- status register + type SR_Register_2 is record + -- Update interrupt flag + UIF : Boolean := False; + -- Capture/compare 1 interrupt flag + CC1IF : Boolean := False; + -- Capture/Compare 2 interrupt flag + CC2IF : Boolean := False; + -- unspecified + Reserved_3_5 : HAL.UInt3 := 16#0#; + -- Trigger interrupt flag + TIF : Boolean := False; + -- unspecified + Reserved_7_8 : HAL.UInt2 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : Boolean := False; + -- Capture/compare 2 overcapture flag + CC2OF : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register_2 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + CC2IF at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TIF at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + CC1OF at 0 range 9 .. 9; + CC2OF at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- event generation register + type EGR_Register_2 is record + -- Write-only. Update generation + UG : Boolean := False; + -- Write-only. Capture/compare 1 generation + CC1G : Boolean := False; + -- Write-only. Capture/compare 2 generation + CC2G : Boolean := False; + -- unspecified + Reserved_3_5 : HAL.UInt3 := 16#0#; + -- Write-only. Trigger generation + TG : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EGR_Register_2 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + CC2G at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TG at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- capture/compare mode register 1 (output mode) + type CCMR1_Output_Register_1 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Output_CC1S_Field := 16#0#; + -- Output Compare 1 fast enable + OC1FE : Boolean := False; + -- Output Compare 1 preload enable + OC1PE : Boolean := False; + -- Output Compare 1 mode + OC1M : CCMR1_Output_OC1M_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Capture/Compare 2 selection + CC2S : CCMR1_Output_CC2S_Field := 16#0#; + -- Output Compare 2 fast enable + OC2FE : Boolean := False; + -- Output Compare 2 preload enable + OC2PE : Boolean := False; + -- Output Compare 2 mode + OC2M : CCMR1_Output_OC2M_Field := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Output_Register_1 use record + CC1S at 0 range 0 .. 1; + OC1FE at 0 range 2 .. 2; + OC1PE at 0 range 3 .. 3; + OC1M at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CC2S at 0 range 8 .. 9; + OC2FE at 0 range 10 .. 10; + OC2PE at 0 range 11 .. 11; + OC2M at 0 range 12 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype CCMR1_Input_IC1F_Field_1 is HAL.UInt3; + subtype CCMR1_Input_IC2F_Field_1 is HAL.UInt3; + + -- capture/compare mode register 1 (input mode) + type CCMR1_Input_Register_1 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Input_CC1S_Field := 16#0#; + -- Input capture 1 prescaler + ICPCS : CCMR1_Input_ICPCS_Field := 16#0#; + -- Input capture 1 filter + IC1F : CCMR1_Input_IC1F_Field_1 := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Capture/Compare 2 selection + CC2S : CCMR1_Input_CC2S_Field := 16#0#; + -- Input capture 2 prescaler + IC2PCS : CCMR1_Input_IC2PCS_Field := 16#0#; + -- Input capture 2 filter + IC2F : CCMR1_Input_IC2F_Field_1 := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Input_Register_1 use record + CC1S at 0 range 0 .. 1; + ICPCS at 0 range 2 .. 3; + IC1F at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CC2S at 0 range 8 .. 9; + IC2PCS at 0 range 10 .. 11; + IC2F at 0 range 12 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register_2 is record + -- Capture/Compare 1 output enable + CC1E : Boolean := False; + -- Capture/Compare 1 output Polarity + CC1P : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : Boolean := False; + -- Capture/Compare 2 output enable + CC2E : Boolean := False; + -- Capture/Compare 2 output Polarity + CC2P : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Capture/Compare 2 output Polarity + CC2NP : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCER_Register_2 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + CC2E at 0 range 4 .. 4; + CC2P at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + CC2NP at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- control register 1 + type CR1_Register_2 is record + -- Counter enable + CEN : Boolean := False; + -- Update disable + UDIS : Boolean := False; + -- Update request source + URS : Boolean := False; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Auto-reload preload enable + ARPE : Boolean := False; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register_2 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_3 is record + -- Update interrupt enable + UIE : Boolean := False; + -- Capture/Compare 1 interrupt enable + CC1IE : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIER_Register_3 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- status register + type SR_Register_3 is record + -- Update interrupt flag + UIF : Boolean := False; + -- Capture/compare 1 interrupt flag + CC1IF : Boolean := False; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register_3 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + CC1OF at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- event generation register + type EGR_Register_3 is record + -- Write-only. Update generation + UG : Boolean := False; + -- Write-only. Capture/compare 1 generation + CC1G : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EGR_Register_3 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- capture/compare mode register 1 (output mode) + type CCMR1_Output_Register_2 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Output_CC1S_Field := 16#0#; + -- Output Compare 1 fast enable + OC1FE : Boolean := False; + -- Output Compare 1 preload enable + OC1PE : Boolean := False; + -- Output Compare 1 mode + OC1M : CCMR1_Output_OC1M_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Output_Register_2 use record + CC1S at 0 range 0 .. 1; + OC1FE at 0 range 2 .. 2; + OC1PE at 0 range 3 .. 3; + OC1M at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- capture/compare mode register 1 (input mode) + type CCMR1_Input_Register_2 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Input_CC1S_Field := 16#0#; + -- Input capture 1 prescaler + ICPCS : CCMR1_Input_ICPCS_Field := 16#0#; + -- Input capture 1 filter + IC1F : CCMR1_Input_IC1F_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCMR1_Input_Register_2 use record + CC1S at 0 range 0 .. 1; + ICPCS at 0 range 2 .. 3; + IC1F at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register_3 is record + -- Capture/Compare 1 output enable + CC1E : Boolean := False; + -- Capture/Compare 1 output Polarity + CC1P : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCER_Register_3 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype OR_RMP_Field is HAL.UInt2; + + -- option register + type OR_Register_2 is record + -- Input 1 remapping capability + RMP : OR_RMP_Field := 16#0#; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OR_Register_2 use record + RMP at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type TIM1_Disc is + (Output, + Input); + + -- Advanced-timers + type TIM1_Peripheral + (Discriminent : TIM1_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register; + -- slave mode control register + SMCR : aliased SMCR_Register; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register; + -- status register + SR : aliased SR_Register; + -- event generation register + EGR : aliased EGR_Register; + -- capture/compare enable register + CCER : aliased CCER_Register; + -- counter + CNT : aliased CNT_Register; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register; + -- repetition counter register + RCR : aliased RCR_Register; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + -- capture/compare register 2 + CCR2 : aliased CCR2_Register; + -- capture/compare register 3 + CCR3 : aliased CCR3_Register; + -- capture/compare register 4 + CCR4 : aliased CCR4_Register; + -- break and dead-time register + BDTR : aliased BDTR_Register; + -- DMA control register + DCR : aliased DCR_Register; + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM1_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + RCR at 16#30# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + BDTR at 16#44# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; + + -- Advanced-timers + TIM1_Periph : aliased TIM1_Peripheral + with Import, Address => TIM1_Base; + + -- Advanced-timers + TIM8_Periph : aliased TIM1_Peripheral + with Import, Address => TIM8_Base; + + type TIM2_Disc is + (Output, + Input); + + -- General purpose timers + type TIM2_Peripheral + (Discriminent : TIM2_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register_1; + -- slave mode control register + SMCR : aliased SMCR_Register; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_1; + -- status register + SR : aliased SR_Register_1; + -- event generation register + EGR : aliased EGR_Register_1; + -- capture/compare enable register + CCER : aliased CCER_Register_1; + -- counter + CNT : aliased CNT_Register_1; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register_1; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register_1; + -- capture/compare register 2 + CCR2 : aliased CCR2_Register_1; + -- capture/compare register 3 + CCR3 : aliased CCR3_Register_1; + -- capture/compare register 4 + CCR4 : aliased CCR4_Register_1; + -- DMA control register + DCR : aliased DCR_Register; + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + -- TIM5 option register + OR_k : aliased OR_Register; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM2_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; + + -- General purpose timers + TIM2_Periph : aliased TIM2_Peripheral + with Import, Address => TIM2_Base; + + type TIM3_Disc is + (Output, + Input); + + -- General purpose timers + type TIM3_Peripheral + (Discriminent : TIM3_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register_1; + -- slave mode control register + SMCR : aliased SMCR_Register; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_1; + -- status register + SR : aliased SR_Register_1; + -- event generation register + EGR : aliased EGR_Register_1; + -- capture/compare enable register + CCER : aliased CCER_Register_1; + -- counter + CNT : aliased CNT_Register_1; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register_1; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register_1; + -- capture/compare register 2 + CCR2 : aliased CCR2_Register_1; + -- capture/compare register 3 + CCR3 : aliased CCR3_Register_1; + -- capture/compare register 4 + CCR4 : aliased CCR4_Register_1; + -- DMA control register + DCR : aliased DCR_Register; + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM3_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; + + -- General purpose timers + TIM3_Periph : aliased TIM3_Peripheral + with Import, Address => TIM3_Base; + + -- General purpose timers + TIM4_Periph : aliased TIM3_Peripheral + with Import, Address => TIM4_Base; + + type TIM5_Disc is + (Output, + Input); + + -- General-purpose-timers + type TIM5_Peripheral + (Discriminent : TIM5_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register; + -- control register 2 + CR2 : aliased CR2_Register_1; + -- slave mode control register + SMCR : aliased SMCR_Register; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_1; + -- status register + SR : aliased SR_Register_1; + -- event generation register + EGR : aliased EGR_Register_1; + -- capture/compare enable register + CCER : aliased CCER_Register_1; + -- counter + CNT : aliased CNT_Register_1; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register_1; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register_1; + -- capture/compare register 2 + CCR2 : aliased CCR2_Register_1; + -- capture/compare register 3 + CCR3 : aliased CCR3_Register_1; + -- capture/compare register 4 + CCR4 : aliased CCR4_Register_1; + -- DMA control register + DCR : aliased DCR_Register; + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + -- TIM5 option register + OR_k : aliased OR_Register_1; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM5_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; + + -- General-purpose-timers + TIM5_Periph : aliased TIM5_Peripheral + with Import, Address => TIM5_Base; + + type TIM9_Disc is + (Output, + Input); + + -- General purpose timers + type TIM9_Peripheral + (Discriminent : TIM9_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register_1; + -- control register 2 + CR2 : aliased CR2_Register_2; + -- slave mode control register + SMCR : aliased SMCR_Register_1; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_2; + -- status register + SR : aliased SR_Register_2; + -- event generation register + EGR : aliased EGR_Register_2; + -- capture/compare enable register + CCER : aliased CCER_Register_2; + -- counter + CNT : aliased CNT_Register; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + -- capture/compare register 2 + CCR2 : aliased CCR2_Register; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_1; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_1; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM9_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + end record; + + -- General purpose timers + TIM9_Periph : aliased TIM9_Peripheral + with Import, Address => TIM9_Base; + + type TIM10_Disc is + (Output, + Input); + + -- General-purpose-timers + type TIM10_Peripheral + (Discriminent : TIM10_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register_2; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_3; + -- status register + SR : aliased SR_Register_3; + -- event generation register + EGR : aliased EGR_Register_3; + -- capture/compare enable register + CCER : aliased CCER_Register_3; + -- counter + CNT : aliased CNT_Register; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM10_Peripheral use record + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + end record; + + -- General-purpose-timers + TIM10_Periph : aliased TIM10_Peripheral + with Import, Address => TIM10_Base; + + type TIM11_Disc is + (Output, + Input); + + -- General-purpose-timers + type TIM11_Peripheral + (Discriminent : TIM11_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register_2; + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_3; + -- status register + SR : aliased SR_Register_3; + -- event generation register + EGR : aliased EGR_Register_3; + -- capture/compare enable register + CCER : aliased CCER_Register_3; + -- counter + CNT : aliased CNT_Register; + -- prescaler + PSC : aliased PSC_Register; + -- auto-reload register + ARR : aliased ARR_Register; + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + -- option register + OR_k : aliased OR_Register_2; + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + end case; + end record + with Unchecked_Union, Volatile; + + for TIM11_Peripheral use record + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + end record; + + -- General-purpose-timers + TIM11_Periph : aliased TIM11_Peripheral + with Import, Address => TIM11_Base; + +end STM32_SVD.TIM; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-usart.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-usart.ads new file mode 100644 index 000000000..4c8222d36 --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-usart.ads @@ -0,0 +1,319 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.USART is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Status register + type SR_Register is record + -- Read-only. Parity error + PE : Boolean := False; + -- Read-only. Framing error + FE : Boolean := False; + -- Read-only. Noise detected flag + NF : Boolean := False; + -- Read-only. Overrun error + ORE : Boolean := False; + -- Read-only. IDLE line detected + IDLE : Boolean := False; + -- Read data register not empty + RXNE : Boolean := False; + -- Transmission complete + TC : Boolean := False; + -- Read-only. Transmit data register empty + TXE : Boolean := False; + -- LIN break detection flag + LBD : Boolean := False; + -- CTS flag + CTS : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#3000#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + PE at 0 range 0 .. 0; + FE at 0 range 1 .. 1; + NF at 0 range 2 .. 2; + ORE at 0 range 3 .. 3; + IDLE at 0 range 4 .. 4; + RXNE at 0 range 5 .. 5; + TC at 0 range 6 .. 6; + TXE at 0 range 7 .. 7; + LBD at 0 range 8 .. 8; + CTS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype DR_DR_Field is HAL.UInt9; + + -- Data register + type DR_Register is record + -- Data value + DR : DR_DR_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DR_Register use record + DR at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype BRR_DIV_Fraction_Field is HAL.UInt4; + subtype BRR_DIV_Mantissa_Field is HAL.UInt12; + + -- Baud rate register + type BRR_Register is record + -- fraction of USARTDIV + DIV_Fraction : BRR_DIV_Fraction_Field := 16#0#; + -- mantissa of USARTDIV + DIV_Mantissa : BRR_DIV_Mantissa_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BRR_Register use record + DIV_Fraction at 0 range 0 .. 3; + DIV_Mantissa at 0 range 4 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Control register 1 + type CR1_Register is record + -- Send break + SBK : Boolean := False; + -- Receiver wakeup + RWU : Boolean := False; + -- Receiver enable + RE : Boolean := False; + -- Transmitter enable + TE : Boolean := False; + -- IDLE interrupt enable + IDLEIE : Boolean := False; + -- RXNE interrupt enable + RXNEIE : Boolean := False; + -- Transmission complete interrupt enable + TCIE : Boolean := False; + -- TXE interrupt enable + TXEIE : Boolean := False; + -- PE interrupt enable + PEIE : Boolean := False; + -- Parity selection + PS : Boolean := False; + -- Parity control enable + PCE : Boolean := False; + -- Wakeup method + WAKE : Boolean := False; + -- Word length + M : Boolean := False; + -- USART enable + UE : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Oversampling mode + OVER8 : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR1_Register use record + SBK at 0 range 0 .. 0; + RWU at 0 range 1 .. 1; + RE at 0 range 2 .. 2; + TE at 0 range 3 .. 3; + IDLEIE at 0 range 4 .. 4; + RXNEIE at 0 range 5 .. 5; + TCIE at 0 range 6 .. 6; + TXEIE at 0 range 7 .. 7; + PEIE at 0 range 8 .. 8; + PS at 0 range 9 .. 9; + PCE at 0 range 10 .. 10; + WAKE at 0 range 11 .. 11; + M at 0 range 12 .. 12; + UE at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + OVER8 at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CR2_ADD_Field is HAL.UInt4; + subtype CR2_STOP_Field is HAL.UInt2; + + -- Control register 2 + type CR2_Register is record + -- Address of the USART node + ADD : CR2_ADD_Field := 16#0#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- lin break detection length + LBDL : Boolean := False; + -- LIN break detection interrupt enable + LBDIE : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Last bit clock pulse + LBCL : Boolean := False; + -- Clock phase + CPHA : Boolean := False; + -- Clock polarity + CPOL : Boolean := False; + -- Clock enable + CLKEN : Boolean := False; + -- STOP bits + STOP : CR2_STOP_Field := 16#0#; + -- LIN mode enable + LINEN : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR2_Register use record + ADD at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LBDL at 0 range 5 .. 5; + LBDIE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + LBCL at 0 range 8 .. 8; + CPHA at 0 range 9 .. 9; + CPOL at 0 range 10 .. 10; + CLKEN at 0 range 11 .. 11; + STOP at 0 range 12 .. 13; + LINEN at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Control register 3 + type CR3_Register is record + -- Error interrupt enable + EIE : Boolean := False; + -- IrDA mode enable + IREN : Boolean := False; + -- IrDA low-power + IRLP : Boolean := False; + -- Half-duplex selection + HDSEL : Boolean := False; + -- Smartcard NACK enable + NACK : Boolean := False; + -- Smartcard mode enable + SCEN : Boolean := False; + -- DMA enable receiver + DMAR : Boolean := False; + -- DMA enable transmitter + DMAT : Boolean := False; + -- RTS enable + RTSE : Boolean := False; + -- CTS enable + CTSE : Boolean := False; + -- CTS interrupt enable + CTSIE : Boolean := False; + -- One sample bit method enable + ONEBIT : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR3_Register use record + EIE at 0 range 0 .. 0; + IREN at 0 range 1 .. 1; + IRLP at 0 range 2 .. 2; + HDSEL at 0 range 3 .. 3; + NACK at 0 range 4 .. 4; + SCEN at 0 range 5 .. 5; + DMAR at 0 range 6 .. 6; + DMAT at 0 range 7 .. 7; + RTSE at 0 range 8 .. 8; + CTSE at 0 range 9 .. 9; + CTSIE at 0 range 10 .. 10; + ONEBIT at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype GTPR_PSC_Field is HAL.UInt8; + subtype GTPR_GT_Field is HAL.UInt8; + + -- Guard time and prescaler register + type GTPR_Register is record + -- Prescaler value + PSC : GTPR_PSC_Field := 16#0#; + -- Guard time value + GT : GTPR_GT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GTPR_Register use record + PSC at 0 range 0 .. 7; + GT at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Universal synchronous asynchronous receiver transmitter + type USART_Peripheral is record + -- Status register + SR : aliased SR_Register; + -- Data register + DR : aliased DR_Register; + -- Baud rate register + BRR : aliased BRR_Register; + -- Control register 1 + CR1 : aliased CR1_Register; + -- Control register 2 + CR2 : aliased CR2_Register; + -- Control register 3 + CR3 : aliased CR3_Register; + -- Guard time and prescaler register + GTPR : aliased GTPR_Register; + end record + with Volatile; + + for USART_Peripheral use record + SR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + BRR at 16#8# range 0 .. 31; + CR1 at 16#C# range 0 .. 31; + CR2 at 16#10# range 0 .. 31; + CR3 at 16#14# range 0 .. 31; + GTPR at 16#18# range 0 .. 31; + end record; + + -- Universal synchronous asynchronous receiver transmitter + USART1_Periph : aliased USART_Peripheral + with Import, Address => USART1_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART2_Periph : aliased USART_Peripheral + with Import, Address => USART2_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART6_Periph : aliased USART_Peripheral + with Import, Address => USART6_Base; + +end STM32_SVD.USART; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-usb_otg_fs.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-usb_otg_fs.ads new file mode 100644 index 000000000..f180dd50b --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-usb_otg_fs.ads @@ -0,0 +1,2063 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.USB_OTG_FS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype FS_DCFG_DSPD_Field is HAL.UInt2; + subtype FS_DCFG_DAD_Field is HAL.UInt7; + subtype FS_DCFG_PFIVL_Field is HAL.UInt2; + + -- OTG_FS device configuration register (OTG_FS_DCFG) + type FS_DCFG_Register is record + -- Device speed + DSPD : FS_DCFG_DSPD_Field := 16#0#; + -- Non-zero-length status OUT handshake + NZLSOHSK : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Device address + DAD : FS_DCFG_DAD_Field := 16#0#; + -- Periodic frame interval + PFIVL : FS_DCFG_PFIVL_Field := 16#0#; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#1100#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DCFG_Register use record + DSPD at 0 range 0 .. 1; + NZLSOHSK at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DAD at 0 range 4 .. 10; + PFIVL at 0 range 11 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype FS_DCTL_TCTL_Field is HAL.UInt3; + + -- OTG_FS device control register (OTG_FS_DCTL) + type FS_DCTL_Register is record + -- Remote wakeup signaling + RWUSIG : Boolean := False; + -- Soft disconnect + SDIS : Boolean := False; + -- Read-only. Global IN NAK status + GINSTS : Boolean := False; + -- Read-only. Global OUT NAK status + GONSTS : Boolean := False; + -- Test control + TCTL : FS_DCTL_TCTL_Field := 16#0#; + -- Set global IN NAK + SGINAK : Boolean := False; + -- Clear global IN NAK + CGINAK : Boolean := False; + -- Set global OUT NAK + SGONAK : Boolean := False; + -- Clear global OUT NAK + CGONAK : Boolean := False; + -- Power-on programming done + POPRGDNE : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DCTL_Register use record + RWUSIG at 0 range 0 .. 0; + SDIS at 0 range 1 .. 1; + GINSTS at 0 range 2 .. 2; + GONSTS at 0 range 3 .. 3; + TCTL at 0 range 4 .. 6; + SGINAK at 0 range 7 .. 7; + CGINAK at 0 range 8 .. 8; + SGONAK at 0 range 9 .. 9; + CGONAK at 0 range 10 .. 10; + POPRGDNE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype FS_DSTS_ENUMSPD_Field is HAL.UInt2; + subtype FS_DSTS_FNSOF_Field is HAL.UInt14; + + -- OTG_FS device status register (OTG_FS_DSTS) + type FS_DSTS_Register is record + -- Read-only. Suspend status + SUSPSTS : Boolean; + -- Read-only. Enumerated speed + ENUMSPD : FS_DSTS_ENUMSPD_Field; + -- Read-only. Erratic error + EERR : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Frame number of the received SOF + FNSOF : FS_DSTS_FNSOF_Field; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DSTS_Register use record + SUSPSTS at 0 range 0 .. 0; + ENUMSPD at 0 range 1 .. 2; + EERR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FNSOF at 0 range 8 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + type FS_DIEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : Boolean := False; + -- Endpoint disabled interrupt mask + EPDM : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Timeout condition mask (Non-isochronous endpoints) + TOM : Boolean := False; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : Boolean := False; + -- IN token received with EP mismatch mask + INEPNMM : Boolean := False; + -- IN endpoint NAK effective mask + INEPNEM : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DIEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + type FS_DOEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : Boolean := False; + -- Endpoint disabled interrupt mask + EPDM : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- SETUP phase done mask + STUPM : Boolean := False; + -- OUT token received when endpoint disabled mask + OTEPDM : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DOEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUPM at 0 range 3 .. 3; + OTEPDM at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype FS_DAINT_IEPINT_Field is HAL.UInt16; + subtype FS_DAINT_OEPINT_Field is HAL.UInt16; + + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + type FS_DAINT_Register is record + -- Read-only. IN endpoint interrupt bits + IEPINT : FS_DAINT_IEPINT_Field; + -- Read-only. OUT endpoint interrupt bits + OEPINT : FS_DAINT_OEPINT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DAINT_Register use record + IEPINT at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype FS_DAINTMSK_IEPM_Field is HAL.UInt16; + subtype FS_DAINTMSK_OEPINT_Field is HAL.UInt16; + + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + type FS_DAINTMSK_Register is record + -- IN EP interrupt mask bits + IEPM : FS_DAINTMSK_IEPM_Field := 16#0#; + -- OUT endpoint interrupt bits + OEPINT : FS_DAINTMSK_OEPINT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DAINTMSK_Register use record + IEPM at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype DVBUSDIS_VBUSDT_Field is HAL.UInt16; + + -- OTG_FS device VBUS discharge time register + type DVBUSDIS_Register is record + -- Device VBUS discharge time + VBUSDT : DVBUSDIS_VBUSDT_Field := 16#17D7#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DVBUSDIS_Register use record + VBUSDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DVBUSPULSE_DVBUSP_Field is HAL.UInt12; + + -- OTG_FS device VBUS pulsing time register + type DVBUSPULSE_Register is record + -- Device VBUS pulsing time + DVBUSP : DVBUSPULSE_DVBUSP_Field := 16#5B8#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DVBUSPULSE_Register use record + DVBUSP at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DIEPEMPMSK_INEPTXFEM_Field is HAL.UInt16; + + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + type DIEPEMPMSK_Register is record + -- IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM : DIEPEMPMSK_INEPTXFEM_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPEMPMSK_Register use record + INEPTXFEM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FS_DIEPCTL0_MPSIZ_Field is HAL.UInt2; + subtype FS_DIEPCTL0_EPTYP_Field is HAL.UInt2; + subtype FS_DIEPCTL0_TXFNUM_Field is HAL.UInt4; + + -- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + type FS_DIEPCTL0_Register is record + -- Maximum packet size + MPSIZ : FS_DIEPCTL0_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_2_14 : HAL.UInt13 := 16#0#; + -- Read-only. USB active endpoint + USBAEP : Boolean := False; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- Read-only. NAK status + NAKSTS : Boolean := False; + -- Read-only. Endpoint type + EPTYP : FS_DIEPCTL0_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- STALL handshake + STALL : Boolean := False; + -- TxFIFO number + TXFNUM : FS_DIEPCTL0_TXFNUM_Field := 16#0#; + -- Write-only. Clear NAK + CNAK : Boolean := False; + -- Write-only. Set NAK + SNAK : Boolean := False; + -- unspecified + Reserved_28_29 : HAL.UInt2 := 16#0#; + -- Read-only. Endpoint disable + EPDIS : Boolean := False; + -- Read-only. Endpoint enable + EPENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DIEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + STALL at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; + end record; + + -- device endpoint-x interrupt register + type DIEPINT_Register is record + -- XFRC + XFRC : Boolean := False; + -- EPDISD + EPDISD : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- TOC + TOC : Boolean := False; + -- ITTXFE + ITTXFE : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- INEPNE + INEPNE : Boolean := False; + -- Read-only. TXFE + TXFE : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOC at 0 range 3 .. 3; + ITTXFE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + INEPNE at 0 range 6 .. 6; + TXFE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DIEPTSIZ0_XFRSIZ_Field is HAL.UInt7; + subtype DIEPTSIZ0_PKTCNT_Field is HAL.UInt2; + + -- device endpoint-0 transfer size register + type DIEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : HAL.UInt12 := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype DTXFSTS_INEPTFSAV_Field is HAL.UInt16; + + -- OTG_FS device IN endpoint transmit FIFO status register + type DTXFSTS_Register is record + -- Read-only. IN endpoint TxFIFO space available + INEPTFSAV : DTXFSTS_INEPTFSAV_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DTXFSTS_Register use record + INEPTFSAV at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DIEPCTL1_MPSIZ_Field is HAL.UInt11; + subtype DIEPCTL1_EPTYP_Field is HAL.UInt2; + subtype DIEPCTL1_TXFNUM_Field is HAL.UInt4; + + -- OTG device endpoint-1 control register + type DIEPCTL1_Register is record + -- MPSIZ + MPSIZ : DIEPCTL1_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- USBAEP + USBAEP : Boolean := False; + -- Read-only. EONUM/DPID + EONUM_DPID : Boolean := False; + -- Read-only. NAKSTS + NAKSTS : Boolean := False; + -- EPTYP + EPTYP : DIEPCTL1_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- Stall + Stall : Boolean := False; + -- TXFNUM + TXFNUM : DIEPCTL1_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : Boolean := False; + -- Write-only. SNAK + SNAK : Boolean := False; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : Boolean := False; + -- Write-only. SODDFRM/SD1PID + SODDFRM_SD1PID : Boolean := False; + -- EPDIS + EPDIS : Boolean := False; + -- EPENA + EPENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPCTL1_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM_SD1PID at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; + end record; + + subtype DIEPTSIZ_XFRSIZ_Field is HAL.UInt19; + subtype DIEPTSIZ_PKTCNT_Field is HAL.UInt10; + subtype DIEPTSIZ_MCNT_Field is HAL.UInt2; + + -- device endpoint-1 transfer size register + type DIEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ_PKTCNT_Field := 16#0#; + -- Multi count + MCNT : DIEPTSIZ_MCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + MCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype DIEPCTL_MPSIZ_Field is HAL.UInt11; + subtype DIEPCTL_EPTYP_Field is HAL.UInt2; + subtype DIEPCTL_TXFNUM_Field is HAL.UInt4; + + -- OTG device endpoint-2 control register + type DIEPCTL_Register is record + -- MPSIZ + MPSIZ : DIEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- USBAEP + USBAEP : Boolean := False; + -- Read-only. EONUM/DPID + EONUM_DPID : Boolean := False; + -- Read-only. NAKSTS + NAKSTS : Boolean := False; + -- EPTYP + EPTYP : DIEPCTL_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- Stall + Stall : Boolean := False; + -- TXFNUM + TXFNUM : DIEPCTL_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : Boolean := False; + -- Write-only. SNAK + SNAK : Boolean := False; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : Boolean := False; + -- Write-only. SODDFRM + SODDFRM : Boolean := False; + -- EPDIS + EPDIS : Boolean := False; + -- EPENA + EPENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; + end record; + + subtype DOEPCTL0_MPSIZ_Field is HAL.UInt2; + subtype DOEPCTL0_EPTYP_Field is HAL.UInt2; + + -- device endpoint-0 control register + type DOEPCTL0_Register is record + -- Read-only. MPSIZ + MPSIZ : DOEPCTL0_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_2_14 : HAL.UInt13 := 16#0#; + -- Read-only. USBAEP + USBAEP : Boolean := True; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- Read-only. NAKSTS + NAKSTS : Boolean := False; + -- Read-only. EPTYP + EPTYP : DOEPCTL0_EPTYP_Field := 16#0#; + -- SNPM + SNPM : Boolean := False; + -- Stall + Stall : Boolean := False; + -- unspecified + Reserved_22_25 : HAL.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : Boolean := False; + -- Write-only. SNAK + SNAK : Boolean := False; + -- unspecified + Reserved_28_29 : HAL.UInt2 := 16#0#; + -- Read-only. EPDIS + EPDIS : Boolean := False; + -- Write-only. EPENA + EPENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; + end record; + + -- device endpoint-0 interrupt register + type DOEPINT_Register is record + -- XFRC + XFRC : Boolean := False; + -- EPDISD + EPDISD : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- STUP + STUP : Boolean := False; + -- OTEPDIS + OTEPDIS : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- B2BSTUP + B2BSTUP : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUP at 0 range 3 .. 3; + OTEPDIS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype DOEPTSIZ0_XFRSIZ_Field is HAL.UInt7; + subtype DOEPTSIZ0_STUPCNT_Field is HAL.UInt2; + + -- device OUT endpoint-0 transfer size register + type DOEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : HAL.UInt12 := 16#0#; + -- Packet count + PKTCNT : Boolean := False; + -- unspecified + Reserved_20_28 : HAL.UInt9 := 16#0#; + -- SETUP packet count + STUPCNT : DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 19; + Reserved_20_28 at 0 range 20 .. 28; + STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype DOEPCTL_MPSIZ_Field is HAL.UInt11; + subtype DOEPCTL_EPTYP_Field is HAL.UInt2; + + -- device endpoint-1 control register + type DOEPCTL_Register is record + -- MPSIZ + MPSIZ : DOEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- USBAEP + USBAEP : Boolean := False; + -- Read-only. EONUM/DPID + EONUM_DPID : Boolean := False; + -- Read-only. NAKSTS + NAKSTS : Boolean := False; + -- EPTYP + EPTYP : DOEPCTL_EPTYP_Field := 16#0#; + -- SNPM + SNPM : Boolean := False; + -- Stall + Stall : Boolean := False; + -- unspecified + Reserved_22_25 : HAL.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : Boolean := False; + -- Write-only. SNAK + SNAK : Boolean := False; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : Boolean := False; + -- Write-only. SODDFRM + SODDFRM : Boolean := False; + -- EPDIS + EPDIS : Boolean := False; + -- EPENA + EPENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; + end record; + + subtype DOEPTSIZ_XFRSIZ_Field is HAL.UInt19; + subtype DOEPTSIZ_PKTCNT_Field is HAL.UInt10; + subtype DOEPTSIZ_RXDPID_STUPCNT_Field is HAL.UInt2; + + -- device OUT endpoint-1 transfer size register + type DOEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DOEPTSIZ_PKTCNT_Field := 16#0#; + -- Received data PID/SETUP packet count + RXDPID_STUPCNT : DOEPTSIZ_RXDPID_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + RXDPID_STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- OTG_FS control and status register (OTG_FS_GOTGCTL) + type FS_GOTGCTL_Register is record + -- Read-only. Session request success + SRQSCS : Boolean := False; + -- Session request + SRQ : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Read-only. Host negotiation success + HNGSCS : Boolean := False; + -- HNP request + HNPRQ : Boolean := False; + -- Host set HNP enable + HSHNPEN : Boolean := False; + -- Device HNP enabled + DHNPEN : Boolean := True; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Read-only. Connector ID status + CIDSTS : Boolean := False; + -- Read-only. Long/short debounce time + DBCT : Boolean := False; + -- Read-only. A-session valid + ASVLD : Boolean := False; + -- Read-only. B-session valid + BSVLD : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GOTGCTL_Register use record + SRQSCS at 0 range 0 .. 0; + SRQ at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + HNGSCS at 0 range 8 .. 8; + HNPRQ at 0 range 9 .. 9; + HSHNPEN at 0 range 10 .. 10; + DHNPEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CIDSTS at 0 range 16 .. 16; + DBCT at 0 range 17 .. 17; + ASVLD at 0 range 18 .. 18; + BSVLD at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- OTG_FS interrupt register (OTG_FS_GOTGINT) + type FS_GOTGINT_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Session end detected + SEDET : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Session request success status change + SRSSCHG : Boolean := False; + -- Host negotiation success status change + HNSSCHG : Boolean := False; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Host negotiation detected + HNGDET : Boolean := False; + -- A-device timeout change + ADTOCHG : Boolean := False; + -- Debounce done + DBCDNE : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GOTGINT_Register use record + Reserved_0_1 at 0 range 0 .. 1; + SEDET at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + SRSSCHG at 0 range 8 .. 8; + HNSSCHG at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + HNGDET at 0 range 17 .. 17; + ADTOCHG at 0 range 18 .. 18; + DBCDNE at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + type FS_GAHBCFG_Register is record + -- Global interrupt mask + GINT : Boolean := False; + -- unspecified + Reserved_1_6 : HAL.UInt6 := 16#0#; + -- TxFIFO empty level + TXFELVL : Boolean := False; + -- Periodic TxFIFO empty level + PTXFELVL : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GAHBCFG_Register use record + GINT at 0 range 0 .. 0; + Reserved_1_6 at 0 range 1 .. 6; + TXFELVL at 0 range 7 .. 7; + PTXFELVL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype FS_GUSBCFG_TOCAL_Field is HAL.UInt3; + subtype FS_GUSBCFG_TRDT_Field is HAL.UInt4; + + -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) + type FS_GUSBCFG_Register is record + -- FS timeout calibration + TOCAL : FS_GUSBCFG_TOCAL_Field := 16#0#; + -- unspecified + Reserved_3_5 : HAL.UInt3 := 16#0#; + -- Write-only. Full Speed serial transceiver select + PHYSEL : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- SRP-capable + SRPCAP : Boolean := False; + -- HNP-capable + HNPCAP : Boolean := True; + -- USB turnaround time + TRDT : FS_GUSBCFG_TRDT_Field := 16#2#; + -- unspecified + Reserved_14_28 : HAL.UInt15 := 16#0#; + -- Force host mode + FHMOD : Boolean := False; + -- Force device mode + FDMOD : Boolean := False; + -- Corrupt Tx packet + CTXPKT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GUSBCFG_Register use record + TOCAL at 0 range 0 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + PHYSEL at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SRPCAP at 0 range 8 .. 8; + HNPCAP at 0 range 9 .. 9; + TRDT at 0 range 10 .. 13; + Reserved_14_28 at 0 range 14 .. 28; + FHMOD at 0 range 29 .. 29; + FDMOD at 0 range 30 .. 30; + CTXPKT at 0 range 31 .. 31; + end record; + + subtype FS_GRSTCTL_TXFNUM_Field is HAL.UInt5; + + -- OTG_FS reset register (OTG_FS_GRSTCTL) + type FS_GRSTCTL_Register is record + -- Core soft reset + CSRST : Boolean := False; + -- HCLK soft reset + HSRST : Boolean := False; + -- Host frame counter reset + FCRST : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- RxFIFO flush + RXFFLSH : Boolean := False; + -- TxFIFO flush + TXFFLSH : Boolean := False; + -- TxFIFO number + TXFNUM : FS_GRSTCTL_TXFNUM_Field := 16#0#; + -- unspecified + Reserved_11_30 : HAL.UInt20 := 16#40000#; + -- Read-only. AHB master idle + AHBIDL : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GRSTCTL_Register use record + CSRST at 0 range 0 .. 0; + HSRST at 0 range 1 .. 1; + FCRST at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + RXFFLSH at 0 range 4 .. 4; + TXFFLSH at 0 range 5 .. 5; + TXFNUM at 0 range 6 .. 10; + Reserved_11_30 at 0 range 11 .. 30; + AHBIDL at 0 range 31 .. 31; + end record; + + -- OTG_FS core interrupt register (OTG_FS_GINTSTS) + type FS_GINTSTS_Register is record + -- Read-only. Current mode of operation + CMOD : Boolean := False; + -- Mode mismatch interrupt + MMIS : Boolean := False; + -- Read-only. OTG interrupt + OTGINT : Boolean := False; + -- Start of frame + SOF : Boolean := False; + -- Read-only. RxFIFO non-empty + RXFLVL : Boolean := False; + -- Read-only. Non-periodic TxFIFO empty + NPTXFE : Boolean := True; + -- Read-only. Global IN non-periodic NAK effective + GINAKEFF : Boolean := False; + -- Read-only. Global OUT NAK effective + GOUTNAKEFF : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Early suspend + ESUSP : Boolean := False; + -- USB suspend + USBSUSP : Boolean := False; + -- USB reset + USBRST : Boolean := False; + -- Enumeration done + ENUMDNE : Boolean := False; + -- Isochronous OUT packet dropped interrupt + ISOODRP : Boolean := False; + -- End of periodic frame interrupt + EOPF : Boolean := False; + -- unspecified + Reserved_16_17 : HAL.UInt2 := 16#0#; + -- Read-only. IN endpoint interrupt + IEPINT : Boolean := False; + -- Read-only. OUT endpoint interrupt + OEPINT : Boolean := False; + -- Incomplete isochronous IN transfer + IISOIXFR : Boolean := False; + -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT + -- transfer(Device mode) + IPXFR_INCOMPISOOUT : Boolean := False; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Read-only. Host port interrupt + HPRTINT : Boolean := False; + -- Read-only. Host channels interrupt + HCINT : Boolean := False; + -- Read-only. Periodic TxFIFO empty + PTXFE : Boolean := True; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Connector ID status change + CIDSCHG : Boolean := False; + -- Disconnect detected interrupt + DISCINT : Boolean := False; + -- Session request/new session detected interrupt + SRQINT : Boolean := False; + -- Resume/remote wakeup detected interrupt + WKUPINT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GINTSTS_Register use record + CMOD at 0 range 0 .. 0; + MMIS at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOF at 0 range 3 .. 3; + RXFLVL at 0 range 4 .. 4; + NPTXFE at 0 range 5 .. 5; + GINAKEFF at 0 range 6 .. 6; + GOUTNAKEFF at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSP at 0 range 10 .. 10; + USBSUSP at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNE at 0 range 13 .. 13; + ISOODRP at 0 range 14 .. 14; + EOPF at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFR at 0 range 20 .. 20; + IPXFR_INCOMPISOOUT at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + HPRTINT at 0 range 24 .. 24; + HCINT at 0 range 25 .. 25; + PTXFE at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHG at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQINT at 0 range 30 .. 30; + WKUPINT at 0 range 31 .. 31; + end record; + + -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) + type FS_GINTMSK_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Mode mismatch interrupt mask + MMISM : Boolean := False; + -- OTG interrupt mask + OTGINT : Boolean := False; + -- Start of frame mask + SOFM : Boolean := False; + -- Receive FIFO non-empty mask + RXFLVLM : Boolean := False; + -- Non-periodic TxFIFO empty mask + NPTXFEM : Boolean := False; + -- Global non-periodic IN NAK effective mask + GINAKEFFM : Boolean := False; + -- Global OUT NAK effective mask + GONAKEFFM : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Early suspend mask + ESUSPM : Boolean := False; + -- USB suspend mask + USBSUSPM : Boolean := False; + -- USB reset mask + USBRST : Boolean := False; + -- Enumeration done mask + ENUMDNEM : Boolean := False; + -- Isochronous OUT packet dropped interrupt mask + ISOODRPM : Boolean := False; + -- End of periodic frame interrupt mask + EOPFM : Boolean := False; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- Endpoint mismatch interrupt mask + EPMISM : Boolean := False; + -- IN endpoints interrupt mask + IEPINT : Boolean := False; + -- OUT endpoints interrupt mask + OEPINT : Boolean := False; + -- Incomplete isochronous IN transfer mask + IISOIXFRM : Boolean := False; + -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous + -- OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM : Boolean := False; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Read-only. Host port interrupt mask + PRTIM : Boolean := False; + -- Host channels interrupt mask + HCIM : Boolean := False; + -- Periodic TxFIFO empty mask + PTXFEM : Boolean := False; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Connector ID status change mask + CIDSCHGM : Boolean := False; + -- Disconnect detected interrupt mask + DISCINT : Boolean := False; + -- Session request/new session detected interrupt mask + SRQIM : Boolean := False; + -- Resume/remote wakeup detected interrupt mask + WUIM : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MMISM at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOFM at 0 range 3 .. 3; + RXFLVLM at 0 range 4 .. 4; + NPTXFEM at 0 range 5 .. 5; + GINAKEFFM at 0 range 6 .. 6; + GONAKEFFM at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSPM at 0 range 10 .. 10; + USBSUSPM at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNEM at 0 range 13 .. 13; + ISOODRPM at 0 range 14 .. 14; + EOPFM at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + EPMISM at 0 range 17 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFRM at 0 range 20 .. 20; + IPXFRM_IISOOXFRM at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PRTIM at 0 range 24 .. 24; + HCIM at 0 range 25 .. 25; + PTXFEM at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHGM at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQIM at 0 range 30 .. 30; + WUIM at 0 range 31 .. 31; + end record; + + subtype FS_GRXSTSR_Device_EPNUM_Field is HAL.UInt4; + subtype FS_GRXSTSR_Device_BCNT_Field is HAL.UInt11; + subtype FS_GRXSTSR_Device_DPID_Field is HAL.UInt2; + subtype FS_GRXSTSR_Device_PKTSTS_Field is HAL.UInt4; + subtype FS_GRXSTSR_Device_FRMNUM_Field is HAL.UInt4; + + -- OTG_FS Receive status debug read(Device mode) + type FS_GRXSTSR_Device_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Device_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Device_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Device_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Device_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Device_FRMNUM_Field; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GRXSTSR_Device_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype FS_GRXSTSR_Host_EPNUM_Field is HAL.UInt4; + subtype FS_GRXSTSR_Host_BCNT_Field is HAL.UInt11; + subtype FS_GRXSTSR_Host_DPID_Field is HAL.UInt2; + subtype FS_GRXSTSR_Host_PKTSTS_Field is HAL.UInt4; + subtype FS_GRXSTSR_Host_FRMNUM_Field is HAL.UInt4; + + -- OTG_FS Receive status debug read(Host mode) + type FS_GRXSTSR_Host_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Host_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Host_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Host_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Host_FRMNUM_Field; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GRXSTSR_Host_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype FS_GRXFSIZ_RXFD_Field is HAL.UInt16; + + -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + type FS_GRXFSIZ_Register is record + -- RxFIFO depth + RXFD : FS_GRXFSIZ_RXFD_Field := 16#200#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GRXFSIZ_Register use record + RXFD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FS_GNPTXFSIZ_Device_TX0FSA_Field is HAL.UInt16; + subtype FS_GNPTXFSIZ_Device_TX0FD_Field is HAL.UInt16; + + -- OTG_FS non-periodic transmit FIFO size register (Device mode) + type FS_GNPTXFSIZ_Device_Register is record + -- Endpoint 0 transmit RAM start address + TX0FSA : FS_GNPTXFSIZ_Device_TX0FSA_Field := 16#200#; + -- Endpoint 0 TxFIFO depth + TX0FD : FS_GNPTXFSIZ_Device_TX0FD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GNPTXFSIZ_Device_Register use record + TX0FSA at 0 range 0 .. 15; + TX0FD at 0 range 16 .. 31; + end record; + + subtype FS_GNPTXFSIZ_Host_NPTXFSA_Field is HAL.UInt16; + subtype FS_GNPTXFSIZ_Host_NPTXFD_Field is HAL.UInt16; + + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + type FS_GNPTXFSIZ_Host_Register is record + -- Non-periodic transmit RAM start address + NPTXFSA : FS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; + -- Non-periodic TxFIFO depth + NPTXFD : FS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GNPTXFSIZ_Host_Register use record + NPTXFSA at 0 range 0 .. 15; + NPTXFD at 0 range 16 .. 31; + end record; + + subtype FS_GNPTXSTS_NPTXFSAV_Field is HAL.UInt16; + subtype FS_GNPTXSTS_NPTQXSAV_Field is HAL.UInt8; + subtype FS_GNPTXSTS_NPTXQTOP_Field is HAL.UInt7; + + -- OTG_FS non-periodic transmit FIFO/queue status register + -- (OTG_FS_GNPTXSTS) + type FS_GNPTXSTS_Register is record + -- Read-only. Non-periodic TxFIFO space available + NPTXFSAV : FS_GNPTXSTS_NPTXFSAV_Field; + -- Read-only. Non-periodic transmit request queue space available + NPTQXSAV : FS_GNPTXSTS_NPTQXSAV_Field; + -- Read-only. Top of the non-periodic transmit request queue + NPTXQTOP : FS_GNPTXSTS_NPTXQTOP_Field; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GNPTXSTS_Register use record + NPTXFSAV at 0 range 0 .. 15; + NPTQXSAV at 0 range 16 .. 23; + NPTXQTOP at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- OTG_FS general core configuration register (OTG_FS_GCCFG) + type FS_GCCFG_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Power down + PWRDWN : Boolean := False; + -- unspecified + Reserved_17_17 : HAL.Bit := 16#0#; + -- Enable the VBUS sensing device + VBUSASEN : Boolean := False; + -- Enable the VBUS sensing device + VBUSBSEN : Boolean := False; + -- SOF output enable + SOFOUTEN : Boolean := False; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_GCCFG_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PWRDWN at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + VBUSASEN at 0 range 18 .. 18; + VBUSBSEN at 0 range 19 .. 19; + SOFOUTEN at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype FS_HPTXFSIZ_PTXSA_Field is HAL.UInt16; + subtype FS_HPTXFSIZ_PTXFSIZ_Field is HAL.UInt16; + + -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + type FS_HPTXFSIZ_Register is record + -- Host periodic TxFIFO start address + PTXSA : FS_HPTXFSIZ_PTXSA_Field := 16#600#; + -- Host periodic TxFIFO depth + PTXFSIZ : FS_HPTXFSIZ_PTXFSIZ_Field := 16#200#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HPTXFSIZ_Register use record + PTXSA at 0 range 0 .. 15; + PTXFSIZ at 0 range 16 .. 31; + end record; + + subtype FS_DIEPTXF_INEPTXSA_Field is HAL.UInt16; + subtype FS_DIEPTXF_INEPTXFD_Field is HAL.UInt16; + + -- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + type FS_DIEPTXF_Register is record + -- IN endpoint FIFO2 transmit RAM start address + INEPTXSA : FS_DIEPTXF_INEPTXSA_Field := 16#400#; + -- IN endpoint TxFIFO depth + INEPTXFD : FS_DIEPTXF_INEPTXFD_Field := 16#200#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_DIEPTXF_Register use record + INEPTXSA at 0 range 0 .. 15; + INEPTXFD at 0 range 16 .. 31; + end record; + + subtype FS_HCFG_FSLSPCS_Field is HAL.UInt2; + + -- OTG_FS host configuration register (OTG_FS_HCFG) + type FS_HCFG_Register is record + -- FS/LS PHY clock select + FSLSPCS : FS_HCFG_FSLSPCS_Field := 16#0#; + -- Read-only. FS- and LS-only support + FSLSS : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HCFG_Register use record + FSLSPCS at 0 range 0 .. 1; + FSLSS at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype HFIR_FRIVL_Field is HAL.UInt16; + + -- OTG_FS Host frame interval register + type HFIR_Register is record + -- Frame interval + FRIVL : HFIR_FRIVL_Field := 16#EA60#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFIR_Register use record + FRIVL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FS_HFNUM_FRNUM_Field is HAL.UInt16; + subtype FS_HFNUM_FTREM_Field is HAL.UInt16; + + -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + type FS_HFNUM_Register is record + -- Read-only. Frame number + FRNUM : FS_HFNUM_FRNUM_Field; + -- Read-only. Frame time remaining + FTREM : FS_HFNUM_FTREM_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HFNUM_Register use record + FRNUM at 0 range 0 .. 15; + FTREM at 0 range 16 .. 31; + end record; + + subtype FS_HPTXSTS_PTXFSAVL_Field is HAL.UInt16; + subtype FS_HPTXSTS_PTXQSAV_Field is HAL.UInt8; + subtype FS_HPTXSTS_PTXQTOP_Field is HAL.UInt8; + + -- OTG_FS_Host periodic transmit FIFO/queue status register + -- (OTG_FS_HPTXSTS) + type FS_HPTXSTS_Register is record + -- Periodic transmit data FIFO space available + PTXFSAVL : FS_HPTXSTS_PTXFSAVL_Field := 16#100#; + -- Read-only. Periodic transmit request queue space available + PTXQSAV : FS_HPTXSTS_PTXQSAV_Field := 16#8#; + -- Read-only. Top of the periodic transmit request queue + PTXQTOP : FS_HPTXSTS_PTXQTOP_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HPTXSTS_Register use record + PTXFSAVL at 0 range 0 .. 15; + PTXQSAV at 0 range 16 .. 23; + PTXQTOP at 0 range 24 .. 31; + end record; + + subtype HAINT_HAINT_Field is HAL.UInt16; + + -- OTG_FS Host all channels interrupt register + type HAINT_Register is record + -- Read-only. Channel interrupts + HAINT : HAINT_HAINT_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HAINT_Register use record + HAINT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype HAINTMSK_HAINTM_Field is HAL.UInt16; + + -- OTG_FS host all channels interrupt mask register + type HAINTMSK_Register is record + -- Channel interrupt mask + HAINTM : HAINTMSK_HAINTM_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HAINTMSK_Register use record + HAINTM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FS_HPRT_PLSTS_Field is HAL.UInt2; + subtype FS_HPRT_PTCTL_Field is HAL.UInt4; + subtype FS_HPRT_PSPD_Field is HAL.UInt2; + + -- OTG_FS host port control and status register (OTG_FS_HPRT) + type FS_HPRT_Register is record + -- Read-only. Port connect status + PCSTS : Boolean := False; + -- Port connect detected + PCDET : Boolean := False; + -- Port enable + PENA : Boolean := False; + -- Port enable/disable change + PENCHNG : Boolean := False; + -- Read-only. Port overcurrent active + POCA : Boolean := False; + -- Port overcurrent change + POCCHNG : Boolean := False; + -- Port resume + PRES : Boolean := False; + -- Port suspend + PSUSP : Boolean := False; + -- Port reset + PRST : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Read-only. Port line status + PLSTS : FS_HPRT_PLSTS_Field := 16#0#; + -- Port power + PPWR : Boolean := False; + -- Port test control + PTCTL : FS_HPRT_PTCTL_Field := 16#0#; + -- Read-only. Port speed + PSPD : FS_HPRT_PSPD_Field := 16#0#; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HPRT_Register use record + PCSTS at 0 range 0 .. 0; + PCDET at 0 range 1 .. 1; + PENA at 0 range 2 .. 2; + PENCHNG at 0 range 3 .. 3; + POCA at 0 range 4 .. 4; + POCCHNG at 0 range 5 .. 5; + PRES at 0 range 6 .. 6; + PSUSP at 0 range 7 .. 7; + PRST at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PLSTS at 0 range 10 .. 11; + PPWR at 0 range 12 .. 12; + PTCTL at 0 range 13 .. 16; + PSPD at 0 range 17 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype FS_HCCHAR_MPSIZ_Field is HAL.UInt11; + subtype FS_HCCHAR_EPNUM_Field is HAL.UInt4; + subtype FS_HCCHAR_EPTYP_Field is HAL.UInt2; + subtype FS_HCCHAR_MCNT_Field is HAL.UInt2; + subtype FS_HCCHAR_DAD_Field is HAL.UInt7; + + -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + type FS_HCCHAR_Register is record + -- Maximum packet size + MPSIZ : FS_HCCHAR_MPSIZ_Field := 16#0#; + -- Endpoint number + EPNUM : FS_HCCHAR_EPNUM_Field := 16#0#; + -- Endpoint direction + EPDIR : Boolean := False; + -- unspecified + Reserved_16_16 : HAL.Bit := 16#0#; + -- Low-speed device + LSDEV : Boolean := False; + -- Endpoint type + EPTYP : FS_HCCHAR_EPTYP_Field := 16#0#; + -- Multicount + MCNT : FS_HCCHAR_MCNT_Field := 16#0#; + -- Device address + DAD : FS_HCCHAR_DAD_Field := 16#0#; + -- Odd frame + ODDFRM : Boolean := False; + -- Channel disable + CHDIS : Boolean := False; + -- Channel enable + CHENA : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HCCHAR_Register use record + MPSIZ at 0 range 0 .. 10; + EPNUM at 0 range 11 .. 14; + EPDIR at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + LSDEV at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + MCNT at 0 range 20 .. 21; + DAD at 0 range 22 .. 28; + ODDFRM at 0 range 29 .. 29; + CHDIS at 0 range 30 .. 30; + CHENA at 0 range 31 .. 31; + end record; + + -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + type FS_HCINT_Register is record + -- Transfer completed + XFRC : Boolean := False; + -- Channel halted + CHH : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- STALL response received interrupt + STALL : Boolean := False; + -- NAK response received interrupt + NAK : Boolean := False; + -- ACK response received/transmitted interrupt + ACK : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Transaction error + TXERR : Boolean := False; + -- Babble error + BBERR : Boolean := False; + -- Frame overrun + FRMOR : Boolean := False; + -- Data toggle error + DTERR : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HCINT_Register use record + XFRC at 0 range 0 .. 0; + CHH at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALL at 0 range 3 .. 3; + NAK at 0 range 4 .. 4; + ACK at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + TXERR at 0 range 7 .. 7; + BBERR at 0 range 8 .. 8; + FRMOR at 0 range 9 .. 9; + DTERR at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + type FS_HCINTMSK_Register is record + -- Transfer completed mask + XFRCM : Boolean := False; + -- Channel halted mask + CHHM : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- STALL response received interrupt mask + STALLM : Boolean := False; + -- NAK response received interrupt mask + NAKM : Boolean := False; + -- ACK response received/transmitted interrupt mask + ACKM : Boolean := False; + -- response received interrupt mask + NYET : Boolean := False; + -- Transaction error mask + TXERRM : Boolean := False; + -- Babble error mask + BBERRM : Boolean := False; + -- Frame overrun mask + FRMORM : Boolean := False; + -- Data toggle error mask + DTERRM : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HCINTMSK_Register use record + XFRCM at 0 range 0 .. 0; + CHHM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALLM at 0 range 3 .. 3; + NAKM at 0 range 4 .. 4; + ACKM at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERRM at 0 range 7 .. 7; + BBERRM at 0 range 8 .. 8; + FRMORM at 0 range 9 .. 9; + DTERRM at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype FS_HCTSIZ_XFRSIZ_Field is HAL.UInt19; + subtype FS_HCTSIZ_PKTCNT_Field is HAL.UInt10; + subtype FS_HCTSIZ_DPID_Field is HAL.UInt2; + + -- OTG_FS host channel-0 transfer size register + type FS_HCTSIZ_Register is record + -- Transfer size + XFRSIZ : FS_HCTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : FS_HCTSIZ_PKTCNT_Field := 16#0#; + -- Data PID + DPID : FS_HCTSIZ_DPID_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_HCTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + DPID at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- OTG_FS power and clock gating control register + type FS_PCGCCTL_Register is record + -- Stop PHY clock + STPPCLK : Boolean := False; + -- Gate HCLK + GATEHCLK : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- PHY Suspended + PHYSUSP : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FS_PCGCCTL_Register use record + STPPCLK at 0 range 0 .. 0; + GATEHCLK at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + PHYSUSP at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- USB on the go full speed + type OTG_FS_DEVICE_Peripheral is record + -- OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG : aliased FS_DCFG_Register; + -- OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL : aliased FS_DCTL_Register; + -- OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS : aliased FS_DSTS_Register; + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + FS_DIEPMSK : aliased FS_DIEPMSK_Register; + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + FS_DOEPMSK : aliased FS_DOEPMSK_Register; + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT : aliased FS_DAINT_Register; + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK : aliased FS_DAINTMSK_Register; + -- OTG_FS device VBUS discharge time register + DVBUSDIS : aliased DVBUSDIS_Register; + -- OTG_FS device VBUS pulsing time register + DVBUSPULSE : aliased DVBUSPULSE_Register; + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK : aliased DIEPEMPMSK_Register; + -- OTG_FS device control IN endpoint 0 control register + -- (OTG_FS_DIEPCTL0) + FS_DIEPCTL0 : aliased FS_DIEPCTL0_Register; + -- device endpoint-x interrupt register + DIEPINT0 : aliased DIEPINT_Register; + -- device endpoint-0 transfer size register + DIEPTSIZ0 : aliased DIEPTSIZ0_Register; + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0 : aliased DTXFSTS_Register; + -- OTG device endpoint-1 control register + DIEPCTL1 : aliased DIEPCTL1_Register; + -- device endpoint-1 interrupt register + DIEPINT1 : aliased DIEPINT_Register; + -- device endpoint-1 transfer size register + DIEPTSIZ1 : aliased DIEPTSIZ_Register; + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1 : aliased DTXFSTS_Register; + -- OTG device endpoint-2 control register + DIEPCTL2 : aliased DIEPCTL_Register; + -- device endpoint-2 interrupt register + DIEPINT2 : aliased DIEPINT_Register; + -- device endpoint-2 transfer size register + DIEPTSIZ2 : aliased DIEPTSIZ_Register; + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2 : aliased DTXFSTS_Register; + -- OTG device endpoint-3 control register + DIEPCTL3 : aliased DIEPCTL_Register; + -- device endpoint-3 interrupt register + DIEPINT3 : aliased DIEPINT_Register; + -- device endpoint-3 transfer size register + DIEPTSIZ3 : aliased DIEPTSIZ_Register; + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3 : aliased DTXFSTS_Register; + -- device endpoint-0 control register + DOEPCTL0 : aliased DOEPCTL0_Register; + -- device endpoint-0 interrupt register + DOEPINT0 : aliased DOEPINT_Register; + -- device OUT endpoint-0 transfer size register + DOEPTSIZ0 : aliased DOEPTSIZ0_Register; + -- device endpoint-1 control register + DOEPCTL1 : aliased DOEPCTL_Register; + -- device endpoint-1 interrupt register + DOEPINT1 : aliased DOEPINT_Register; + -- device OUT endpoint-1 transfer size register + DOEPTSIZ1 : aliased DOEPTSIZ_Register; + -- device endpoint-2 control register + DOEPCTL2 : aliased DOEPCTL_Register; + -- device endpoint-2 interrupt register + DOEPINT2 : aliased DOEPINT_Register; + -- device OUT endpoint-2 transfer size register + DOEPTSIZ2 : aliased DOEPTSIZ_Register; + -- device endpoint-3 control register + DOEPCTL3 : aliased DOEPCTL_Register; + -- device endpoint-3 interrupt register + DOEPINT3 : aliased DOEPINT_Register; + -- device OUT endpoint-3 transfer size register + DOEPTSIZ3 : aliased DOEPTSIZ_Register; + end record + with Volatile; + + for OTG_FS_DEVICE_Peripheral use record + FS_DCFG at 16#0# range 0 .. 31; + FS_DCTL at 16#4# range 0 .. 31; + FS_DSTS at 16#8# range 0 .. 31; + FS_DIEPMSK at 16#10# range 0 .. 31; + FS_DOEPMSK at 16#14# range 0 .. 31; + FS_DAINT at 16#18# range 0 .. 31; + FS_DAINTMSK at 16#1C# range 0 .. 31; + DVBUSDIS at 16#28# range 0 .. 31; + DVBUSPULSE at 16#2C# range 0 .. 31; + DIEPEMPMSK at 16#34# range 0 .. 31; + FS_DIEPCTL0 at 16#100# range 0 .. 31; + DIEPINT0 at 16#108# range 0 .. 31; + DIEPTSIZ0 at 16#110# range 0 .. 31; + DTXFSTS0 at 16#118# range 0 .. 31; + DIEPCTL1 at 16#120# range 0 .. 31; + DIEPINT1 at 16#128# range 0 .. 31; + DIEPTSIZ1 at 16#130# range 0 .. 31; + DTXFSTS1 at 16#138# range 0 .. 31; + DIEPCTL2 at 16#140# range 0 .. 31; + DIEPINT2 at 16#148# range 0 .. 31; + DIEPTSIZ2 at 16#150# range 0 .. 31; + DTXFSTS2 at 16#158# range 0 .. 31; + DIEPCTL3 at 16#160# range 0 .. 31; + DIEPINT3 at 16#168# range 0 .. 31; + DIEPTSIZ3 at 16#170# range 0 .. 31; + DTXFSTS3 at 16#178# range 0 .. 31; + DOEPCTL0 at 16#300# range 0 .. 31; + DOEPINT0 at 16#308# range 0 .. 31; + DOEPTSIZ0 at 16#310# range 0 .. 31; + DOEPCTL1 at 16#320# range 0 .. 31; + DOEPINT1 at 16#328# range 0 .. 31; + DOEPTSIZ1 at 16#330# range 0 .. 31; + DOEPCTL2 at 16#340# range 0 .. 31; + DOEPINT2 at 16#348# range 0 .. 31; + DOEPTSIZ2 at 16#350# range 0 .. 31; + DOEPCTL3 at 16#360# range 0 .. 31; + DOEPINT3 at 16#368# range 0 .. 31; + DOEPTSIZ3 at 16#370# range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_DEVICE_Periph : aliased OTG_FS_DEVICE_Peripheral + with Import, Address => OTG_FS_DEVICE_Base; + + type OTG_FS_GLOBAL_Disc is + (Device, + Host); + + -- USB on the go full speed + type OTG_FS_GLOBAL_Peripheral + (Discriminent : OTG_FS_GLOBAL_Disc := Device) + is record + -- OTG_FS control and status register (OTG_FS_GOTGCTL) + FS_GOTGCTL : aliased FS_GOTGCTL_Register; + -- OTG_FS interrupt register (OTG_FS_GOTGINT) + FS_GOTGINT : aliased FS_GOTGINT_Register; + -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + FS_GAHBCFG : aliased FS_GAHBCFG_Register; + -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) + FS_GUSBCFG : aliased FS_GUSBCFG_Register; + -- OTG_FS reset register (OTG_FS_GRSTCTL) + FS_GRSTCTL : aliased FS_GRSTCTL_Register; + -- OTG_FS core interrupt register (OTG_FS_GINTSTS) + FS_GINTSTS : aliased FS_GINTSTS_Register; + -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) + FS_GINTMSK : aliased FS_GINTMSK_Register; + -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + FS_GRXFSIZ : aliased FS_GRXFSIZ_Register; + -- OTG_FS non-periodic transmit FIFO/queue status register + -- (OTG_FS_GNPTXSTS) + FS_GNPTXSTS : aliased FS_GNPTXSTS_Register; + -- OTG_FS general core configuration register (OTG_FS_GCCFG) + FS_GCCFG : aliased FS_GCCFG_Register; + -- core ID register + FS_CID : aliased HAL.UInt32; + -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + FS_HPTXFSIZ : aliased FS_HPTXFSIZ_Register; + -- OTG_FS device IN endpoint transmit FIFO size register + -- (OTG_FS_DIEPTXF2) + FS_DIEPTXF1 : aliased FS_DIEPTXF_Register; + -- OTG_FS device IN endpoint transmit FIFO size register + -- (OTG_FS_DIEPTXF3) + FS_DIEPTXF2 : aliased FS_DIEPTXF_Register; + -- OTG_FS device IN endpoint transmit FIFO size register + -- (OTG_FS_DIEPTXF4) + FS_DIEPTXF3 : aliased FS_DIEPTXF_Register; + case Discriminent is + when Device => + -- OTG_FS Receive status debug read(Device mode) + FS_GRXSTSR_Device : aliased FS_GRXSTSR_Device_Register; + -- OTG_FS non-periodic transmit FIFO size register (Device mode) + FS_GNPTXFSIZ_Device : aliased FS_GNPTXFSIZ_Device_Register; + when Host => + -- OTG_FS Receive status debug read(Host mode) + FS_GRXSTSR_Host : aliased FS_GRXSTSR_Host_Register; + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + FS_GNPTXFSIZ_Host : aliased FS_GNPTXFSIZ_Host_Register; + end case; + end record + with Unchecked_Union, Volatile; + + for OTG_FS_GLOBAL_Peripheral use record + FS_GOTGCTL at 16#0# range 0 .. 31; + FS_GOTGINT at 16#4# range 0 .. 31; + FS_GAHBCFG at 16#8# range 0 .. 31; + FS_GUSBCFG at 16#C# range 0 .. 31; + FS_GRSTCTL at 16#10# range 0 .. 31; + FS_GINTSTS at 16#14# range 0 .. 31; + FS_GINTMSK at 16#18# range 0 .. 31; + FS_GRXFSIZ at 16#24# range 0 .. 31; + FS_GNPTXSTS at 16#2C# range 0 .. 31; + FS_GCCFG at 16#38# range 0 .. 31; + FS_CID at 16#3C# range 0 .. 31; + FS_HPTXFSIZ at 16#100# range 0 .. 31; + FS_DIEPTXF1 at 16#104# range 0 .. 31; + FS_DIEPTXF2 at 16#108# range 0 .. 31; + FS_DIEPTXF3 at 16#10C# range 0 .. 31; + FS_GRXSTSR_Device at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Device at 16#28# range 0 .. 31; + FS_GRXSTSR_Host at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Host at 16#28# range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_GLOBAL_Periph : aliased OTG_FS_GLOBAL_Peripheral + with Import, Address => OTG_FS_GLOBAL_Base; + + -- USB on the go full speed + type OTG_FS_HOST_Peripheral is record + -- OTG_FS host configuration register (OTG_FS_HCFG) + FS_HCFG : aliased FS_HCFG_Register; + -- OTG_FS Host frame interval register + HFIR : aliased HFIR_Register; + -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + FS_HFNUM : aliased FS_HFNUM_Register; + -- OTG_FS_Host periodic transmit FIFO/queue status register + -- (OTG_FS_HPTXSTS) + FS_HPTXSTS : aliased FS_HPTXSTS_Register; + -- OTG_FS Host all channels interrupt register + HAINT : aliased HAINT_Register; + -- OTG_FS host all channels interrupt mask register + HAINTMSK : aliased HAINTMSK_Register; + -- OTG_FS host port control and status register (OTG_FS_HPRT) + FS_HPRT : aliased FS_HPRT_Register; + -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + FS_HCCHAR0 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + FS_HCINT0 : aliased FS_HCINT_Register; + -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + FS_HCINTMSK0 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-0 transfer size register + FS_HCTSIZ0 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) + FS_HCCHAR1 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) + FS_HCINT1 : aliased FS_HCINT_Register; + -- OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) + FS_HCINTMSK1 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-1 transfer size register + FS_HCTSIZ1 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) + FS_HCCHAR2 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) + FS_HCINT2 : aliased FS_HCINT_Register; + -- OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) + FS_HCINTMSK2 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-2 transfer size register + FS_HCTSIZ2 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) + FS_HCCHAR3 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) + FS_HCINT3 : aliased FS_HCINT_Register; + -- OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) + FS_HCINTMSK3 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-3 transfer size register + FS_HCTSIZ3 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) + FS_HCCHAR4 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) + FS_HCINT4 : aliased FS_HCINT_Register; + -- OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) + FS_HCINTMSK4 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-x transfer size register + FS_HCTSIZ4 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) + FS_HCCHAR5 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) + FS_HCINT5 : aliased FS_HCINT_Register; + -- OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) + FS_HCINTMSK5 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-5 transfer size register + FS_HCTSIZ5 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) + FS_HCCHAR6 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) + FS_HCINT6 : aliased FS_HCINT_Register; + -- OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) + FS_HCINTMSK6 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-6 transfer size register + FS_HCTSIZ6 : aliased FS_HCTSIZ_Register; + -- OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) + FS_HCCHAR7 : aliased FS_HCCHAR_Register; + -- OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) + FS_HCINT7 : aliased FS_HCINT_Register; + -- OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) + FS_HCINTMSK7 : aliased FS_HCINTMSK_Register; + -- OTG_FS host channel-7 transfer size register + FS_HCTSIZ7 : aliased FS_HCTSIZ_Register; + end record + with Volatile; + + for OTG_FS_HOST_Peripheral use record + FS_HCFG at 16#0# range 0 .. 31; + HFIR at 16#4# range 0 .. 31; + FS_HFNUM at 16#8# range 0 .. 31; + FS_HPTXSTS at 16#10# range 0 .. 31; + HAINT at 16#14# range 0 .. 31; + HAINTMSK at 16#18# range 0 .. 31; + FS_HPRT at 16#40# range 0 .. 31; + FS_HCCHAR0 at 16#100# range 0 .. 31; + FS_HCINT0 at 16#108# range 0 .. 31; + FS_HCINTMSK0 at 16#10C# range 0 .. 31; + FS_HCTSIZ0 at 16#110# range 0 .. 31; + FS_HCCHAR1 at 16#120# range 0 .. 31; + FS_HCINT1 at 16#128# range 0 .. 31; + FS_HCINTMSK1 at 16#12C# range 0 .. 31; + FS_HCTSIZ1 at 16#130# range 0 .. 31; + FS_HCCHAR2 at 16#140# range 0 .. 31; + FS_HCINT2 at 16#148# range 0 .. 31; + FS_HCINTMSK2 at 16#14C# range 0 .. 31; + FS_HCTSIZ2 at 16#150# range 0 .. 31; + FS_HCCHAR3 at 16#160# range 0 .. 31; + FS_HCINT3 at 16#168# range 0 .. 31; + FS_HCINTMSK3 at 16#16C# range 0 .. 31; + FS_HCTSIZ3 at 16#170# range 0 .. 31; + FS_HCCHAR4 at 16#180# range 0 .. 31; + FS_HCINT4 at 16#188# range 0 .. 31; + FS_HCINTMSK4 at 16#18C# range 0 .. 31; + FS_HCTSIZ4 at 16#190# range 0 .. 31; + FS_HCCHAR5 at 16#1A0# range 0 .. 31; + FS_HCINT5 at 16#1A8# range 0 .. 31; + FS_HCINTMSK5 at 16#1AC# range 0 .. 31; + FS_HCTSIZ5 at 16#1B0# range 0 .. 31; + FS_HCCHAR6 at 16#1C0# range 0 .. 31; + FS_HCINT6 at 16#1C8# range 0 .. 31; + FS_HCINTMSK6 at 16#1CC# range 0 .. 31; + FS_HCTSIZ6 at 16#1D0# range 0 .. 31; + FS_HCCHAR7 at 16#1E0# range 0 .. 31; + FS_HCINT7 at 16#1E8# range 0 .. 31; + FS_HCINTMSK7 at 16#1EC# range 0 .. 31; + FS_HCTSIZ7 at 16#1F0# range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_HOST_Periph : aliased OTG_FS_HOST_Peripheral + with Import, Address => OTG_FS_HOST_Base; + + -- USB on the go full speed + type OTG_FS_PWRCLK_Peripheral is record + -- OTG_FS power and clock gating control register + FS_PCGCCTL : aliased FS_PCGCCTL_Register; + end record + with Volatile; + + for OTG_FS_PWRCLK_Peripheral use record + FS_PCGCCTL at 0 range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_PWRCLK_Periph : aliased OTG_FS_PWRCLK_Peripheral + with Import, Address => OTG_FS_PWRCLK_Base; + +end STM32_SVD.USB_OTG_FS; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd-wwdg.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd-wwdg.ads new file mode 100644 index 000000000..d309f0e2c --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd-wwdg.ads @@ -0,0 +1,124 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package STM32_SVD.WWDG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CR_T_Field is HAL.UInt7; + + -- Control register + type CR_Register is record + -- 7-bit counter (MSB to LSB) + T : CR_T_Field := 16#7F#; + -- Activation bit + WDGA : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CR_Register use record + T at 0 range 0 .. 6; + WDGA at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CFR_W_Field is HAL.UInt7; + + -- CFR_WDGTB array + type CFR_WDGTB_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CFR_WDGTB + type CFR_WDGTB_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WDGTB as a value + Val : HAL.UInt2; + when True => + -- WDGTB as an array + Arr : CFR_WDGTB_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CFR_WDGTB_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Configuration register + type CFR_Register is record + -- 7-bit window value + W : CFR_W_Field := 16#7F#; + -- Timer base + WDGTB : CFR_WDGTB_Field := (As_Array => False, Val => 16#0#); + -- Early wakeup interrupt + EWI : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFR_Register use record + W at 0 range 0 .. 6; + WDGTB at 0 range 7 .. 8; + EWI at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- Status register + type SR_Register is record + -- Early wakeup interrupt flag + EWIF : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SR_Register use record + EWIF at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Window watchdog + type WWDG_Peripheral is record + -- Control register + CR : aliased CR_Register; + -- Configuration register + CFR : aliased CFR_Register; + -- Status register + SR : aliased SR_Register; + end record + with Volatile; + + for WWDG_Peripheral use record + CR at 16#0# range 0 .. 31; + CFR at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; + end record; + + -- Window watchdog + WWDG_Periph : aliased WWDG_Peripheral + with Import, Address => WWDG_Base; + +end STM32_SVD.WWDG; diff --git a/arch/ARM/STM32/svd/stm32f401/stm32_svd.ads b/arch/ARM/STM32/svd/stm32f401/stm32_svd.ads new file mode 100644 index 000000000..fc89d7e3b --- /dev/null +++ b/arch/ARM/STM32/svd/stm32f401/stm32_svd.ads @@ -0,0 +1,72 @@ +-- This spec has been automatically generated from STM32F401.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with System; + +-- STM32F401 +package STM32_SVD is + pragma Preelaborate; + + -------------------- + -- Base addresses -- + -------------------- + + ADC_Common_Base : constant System.Address := System'To_Address (16#40012300#); + ADC1_Base : constant System.Address := System'To_Address (16#40012000#); + CRC_Base : constant System.Address := System'To_Address (16#40023000#); + DBG_Base : constant System.Address := System'To_Address (16#E0042000#); + EXTI_Base : constant System.Address := System'To_Address (16#40013C00#); + FLASH_Base : constant System.Address := System'To_Address (16#40023C00#); + IWDG_Base : constant System.Address := System'To_Address (16#40003000#); + OTG_FS_DEVICE_Base : constant System.Address := System'To_Address (16#50000800#); + OTG_FS_GLOBAL_Base : constant System.Address := System'To_Address (16#50000000#); + OTG_FS_HOST_Base : constant System.Address := System'To_Address (16#50000400#); + OTG_FS_PWRCLK_Base : constant System.Address := System'To_Address (16#50000E00#); + PWR_Base : constant System.Address := System'To_Address (16#40007000#); + RCC_Base : constant System.Address := System'To_Address (16#40023800#); + RTC_Base : constant System.Address := System'To_Address (16#40002800#); + SDIO_Base : constant System.Address := System'To_Address (16#40012C00#); + SYSCFG_Base : constant System.Address := System'To_Address (16#40013800#); + TIM1_Base : constant System.Address := System'To_Address (16#40010000#); + TIM8_Base : constant System.Address := System'To_Address (16#40010400#); + TIM10_Base : constant System.Address := System'To_Address (16#40014400#); + TIM11_Base : constant System.Address := System'To_Address (16#40014800#); + TIM2_Base : constant System.Address := System'To_Address (16#40000000#); + TIM3_Base : constant System.Address := System'To_Address (16#40000400#); + TIM4_Base : constant System.Address := System'To_Address (16#40000800#); + TIM5_Base : constant System.Address := System'To_Address (16#40000C00#); + TIM9_Base : constant System.Address := System'To_Address (16#40014000#); + USART1_Base : constant System.Address := System'To_Address (16#40011000#); + USART2_Base : constant System.Address := System'To_Address (16#40004400#); + USART6_Base : constant System.Address := System'To_Address (16#40011400#); + WWDG_Base : constant System.Address := System'To_Address (16#40002C00#); + DMA2_Base : constant System.Address := System'To_Address (16#40026400#); + DMA1_Base : constant System.Address := System'To_Address (16#40026000#); + GPIOH_Base : constant System.Address := System'To_Address (16#40021C00#); + GPIOE_Base : constant System.Address := System'To_Address (16#40021000#); + GPIOD_Base : constant System.Address := System'To_Address (16#40020C00#); + GPIOC_Base : constant System.Address := System'To_Address (16#40020800#); + GPIOB_Base : constant System.Address := System'To_Address (16#40020400#); + GPIOA_Base : constant System.Address := System'To_Address (16#40020000#); + I2C3_Base : constant System.Address := System'To_Address (16#40005C00#); + I2C2_Base : constant System.Address := System'To_Address (16#40005800#); + I2C1_Base : constant System.Address := System'To_Address (16#40005400#); + I2S2ext_Base : constant System.Address := System'To_Address (16#40003400#); + I2S3ext_Base : constant System.Address := System'To_Address (16#40004000#); + SPI1_Base : constant System.Address := System'To_Address (16#40013000#); + SPI2_Base : constant System.Address := System'To_Address (16#40003800#); + SPI3_Base : constant System.Address := System'To_Address (16#40003C00#); + SPI4_Base : constant System.Address := System'To_Address (16#40013400#); + NVIC_Base : constant System.Address := System'To_Address (16#E000E100#); + FPU_Base : constant System.Address := System'To_Address (16#E000EF34#); + MPU_Base : constant System.Address := System'To_Address (16#E000ED90#); + STK_Base : constant System.Address := System'To_Address (16#E000E010#); + SCB_Base : constant System.Address := System'To_Address (16#E000ED00#); + NVIC_STIR_Base : constant System.Address := System'To_Address (16#E000EF00#); + FPU_CPACR_Base : constant System.Address := System'To_Address (16#E000ED88#); + SCB_ACTRL_Base : constant System.Address := System'To_Address (16#E000E008#); + +end STM32_SVD; diff --git a/arch/svd.mk b/arch/svd.mk index 22dc18d31..081d26b01 100644 --- a/arch/svd.mk +++ b/arch/svd.mk @@ -9,6 +9,7 @@ all: svd svd: rm -rf $(STM_DIR)/stm32* $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ST/STM32F40x.svd --boolean -o $(STM_DIR)/stm32f40x -p STM32_SVD --base-types-package HAL --gen-uint-always + $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ST/STM32F401.svd --boolean -o $(STM_DIR)/stm32f401 -p STM32_SVD --base-types-package HAL --gen-uint-always $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ST/STM32F429x.svd --boolean -o $(STM_DIR)/stm32f429x -p STM32_SVD --base-types-package HAL --gen-uint-always $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ST/STM32F46_79x.svd --boolean -o $(STM_DIR)/stm32f46_79x -p STM32_SVD --base-types-package HAL --gen-uint-always $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ST/STM32F7x.svd --boolean -o $(STM_DIR)/stm32f7x -p STM32_SVD --base-types-package HAL --gen-uint-always diff --git a/boards/nucleo_f401re/nucleo_f401re_full.gpr b/boards/nucleo_f401re/nucleo_f401re_full.gpr new file mode 100644 index 000000000..ed9cc7b6b --- /dev/null +++ b/boards/nucleo_f401re/nucleo_f401re_full.gpr @@ -0,0 +1,138 @@ +-- This project file was generated by the Ada_Drivers_Library project wizard script +library project NUCLEO_F401RE_Full is + + type Build_Type is ("Debug", "Production"); + Build : Build_Type := external ("ADL_BUILD", "Debug"); + + type Build_Checks_Type is ("Disabled", "Enabled"); + Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled"); + + -- Target architecture + Target := Project'Target; + + -- Callgraph info is not available on all architectures + Callgraph_Switch := (); + case Target is + when "riscv32-unknown-elf" => null; + when others => Callgraph_Switch := ("-fcallgraph-info=su"); + end case; + + Build_Checks_Switches := (); + case Build_Checks is + when "Disabled" => null; + when others => + Build_Checks_Switches := + ("-gnaty", "-gnatyM120", "-gnatyO", -- Style checks + "-gnatwe"); -- Warnings as errors + end case; + + package Compiler is + case Build is + when "Production" => + for Default_Switches ("Ada") use + ("-O3", -- Optimization + "-gnatp", -- Supress checks + "-gnatn"); -- Enable inlining + when "Debug" => + for Default_Switches ("Ada") use + ("-O0", -- No optimization + "-gnata") -- Enable assertions + & Callgraph_Switch; + end case; + + for Default_Switches ("ada") use Compiler'Default_Switches ("Ada") & + Callgraph_Switch & + Build_Checks_Switches & + ("-g", -- Debug info + "-gnatwa", -- All warnings + "-gnatw_A", -- Turn off warnings for anonymous allocators + "-gnatQ", -- Don't quit. Generate ALI and tree files even if illegalities + "-gnatw.X", -- Disable warnings for No_Exception_Propagation + "-ffunction-sections", -- Create a linker section for each function + "-fdata-sections"); -- Create a linker section for each data + end Compiler; + + + for Languages use ("Ada"); + for Create_Missing_Dirs use "True"; + for Object_Dir use "obj/full_" & Build; + for Library_Dir use "obj/full_lib_" & Build; + for Library_Kind use "static"; + for Library_Name use "ada_drivers_library"; + + Linker_Switches := (); + for Target use "arm-eabi"; + for Runtime ("Ada") use "ravenscar-full-nucleo_f401re"; + + package Device_Configuration is + for CPU_Name use "ARM Cortex-M4F"; + for Number_Of_Interrupts use "0"; + end Device_Configuration; + + Vendor := "STMicro"; -- From board definition + Max_Mount_Points := "2"; -- From default value + Max_Mount_Name_Length := "128"; -- From default value + Runtime_Profile := "ravenscar-full"; -- From command line + Device_Name := "STM32F401RE"; -- From board definition + Device_Family := "STM32F4"; -- From board definition + Has_Ravenscar_SFP_Runtime := "True"; -- From board definition + Runtime_Name := "ravenscar-full-nucleo-f401re"; -- From default value + Has_Ravenscar_Full_Runtime := "True"; -- From board definition + CPU_Core := "ARM Cortex-M4F"; -- From mcu definition + Board := "NUCLEO_F401RE"; -- From command line + Has_ZFP_Runtime := "False"; -- From board definition + Number_Of_Interrupts := "0"; -- From default value + High_Speed_External_Clock := "8000000"; -- From board definition + Use_Startup_Gen := "False"; -- From command line + Max_Path_Length := "1024"; -- From default value + Runtime_Name_Suffix := "stm32f4"; -- From board definition + Architecture := "ARM"; -- From board definition + + -- Project source directories + Src_Dirs_Root := "../.."; + for Source_Dirs use ( + Src_Dirs_Root & "/hal/src/", -- From HAL config + Src_Dirs_Root & "/boards/stm32_common/nucleo_f401re/", -- From board definition + Src_Dirs_Root & "/boards/stm32_common/common/", -- From board definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm4f", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f401/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f401", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/dma/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/dma_interrupts/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/crc_stm32f4/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/i2c_stm32f4", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/power_control_stm32f4", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/uart_stm32f401/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/sd/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/sd/sdio/", -- From MCU definition + Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config + Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config + Src_Dirs_Root & "/middleware/src/utils", -- From middleware config + Src_Dirs_Root & "/middleware/src/audio", -- From middleware config + Src_Dirs_Root & "/middleware/src/monitor", -- From middleware config + Src_Dirs_Root & "/middleware/src/bitmap", -- From middleware config + Src_Dirs_Root & "/middleware/src/command_line", -- From middleware config + Src_Dirs_Root & "/middleware/src/sdmmc", -- From middleware config + Src_Dirs_Root & "/middleware/src/neopixel", -- From middleware config + Src_Dirs_Root & "/middleware/src/ravenscar-common", -- From middleware config + Src_Dirs_Root & "/components/src/**", -- From components config + "src/full/"); + + for Excluded_Source_Files use ( + "stm32-rng.ads", + "stm32-rng.adb", + "stm32-rng-interrupts.adb", + "stm32-rng-interrupts.ads", + "stm32-dac.ads", + "stm32-dac.adb", + "stm32-dcmi.ads", + "stm32-dcmi.adb", + "stm32-rng-polling.adb", + "stm32-rng-polling.ads" + ); +end NUCLEO_F401RE_Full; diff --git a/boards/nucleo_f401re/nucleo_f401re_sfp.gpr b/boards/nucleo_f401re/nucleo_f401re_sfp.gpr new file mode 100644 index 000000000..d8b174450 --- /dev/null +++ b/boards/nucleo_f401re/nucleo_f401re_sfp.gpr @@ -0,0 +1,139 @@ +-- This project file was generated by the Ada_Drivers_Library project wizard script +library project NUCLEO_F401RE_SFP is + + type Build_Type is ("Debug", "Production"); + Build : Build_Type := external ("ADL_BUILD", "Debug"); + + type Build_Checks_Type is ("Disabled", "Enabled"); + Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled"); + + -- Target architecture + Target := Project'Target; + + -- Callgraph info is not available on all architectures + Callgraph_Switch := (); + case Target is + when "riscv32-unknown-elf" => null; + when others => Callgraph_Switch := ("-fcallgraph-info=su"); + end case; + + Build_Checks_Switches := (); + case Build_Checks is + when "Disabled" => null; + when others => + Build_Checks_Switches := + ("-gnaty", "-gnatyM120", "-gnatyO", -- Style checks + "-gnatwe"); -- Warnings as errors + end case; + + package Compiler is + case Build is + when "Production" => + for Default_Switches ("Ada") use + ("-O3", -- Optimization + "-gnatp", -- Supress checks + "-gnatn"); -- Enable inlining + when "Debug" => + for Default_Switches ("Ada") use + ("-O0", -- No optimization + "-gnata") -- Enable assertions + & Callgraph_Switch; + end case; + + for Default_Switches ("ada") use Compiler'Default_Switches ("Ada") & + Callgraph_Switch & + Build_Checks_Switches & + ("-g", -- Debug info + "-gnatwa", -- All warnings + "-gnatw_A", -- Turn off warnings for anonymous allocators + "-gnatQ", -- Don't quit. Generate ALI and tree files even if illegalities + "-gnatw.X", -- Disable warnings for No_Exception_Propagation + "-ffunction-sections", -- Create a linker section for each function + "-fdata-sections"); -- Create a linker section for each data + end Compiler; + + + for Languages use ("Ada"); + for Create_Missing_Dirs use "True"; + for Object_Dir use "obj/sfp_" & Build; + for Library_Dir use "obj/sfp_lib_" & Build; + for Library_Kind use "static"; + for Library_Name use "ada_drivers_library"; + + Linker_Switches := (); + for Target use "arm-eabi"; + for Runtime ("Ada") use "ravenscar-sfp-nucleo_f401re"; + + package Device_Configuration is + for CPU_Name use "ARM Cortex-M4F"; + for Number_Of_Interrupts use "0"; + end Device_Configuration; + + Vendor := "STMicro"; -- From board definition + Max_Mount_Points := "2"; -- From default value + Max_Mount_Name_Length := "128"; -- From default value + Runtime_Profile := "ravenscar-sfp"; -- From command line + Device_Name := "STM32F401RE"; -- From board definition + Device_Family := "STM32F4"; -- From board definition + Has_Ravenscar_SFP_Runtime := "True"; -- From board definition + Runtime_Name := "ravenscar-sfp-nucleo_f401re"; -- From default value + Has_Ravenscar_Full_Runtime := "True"; -- From board definition + CPU_Core := "ARM Cortex-M4F"; -- From mcu definition + Board := "NUCLEO_F401RE"; -- From command line + Has_ZFP_Runtime := "False"; -- From board definition + Number_Of_Interrupts := "0"; -- From default value + High_Speed_External_Clock := "8000000"; -- From board definition + Use_Startup_Gen := "False"; -- From command line + Max_Path_Length := "1024"; -- From default value + Runtime_Name_Suffix := "nucleo_f401re"; -- From board definition + Architecture := "ARM"; -- From board definition + + -- Project source directories + Src_Dirs_Root := "../.."; + for Source_Dirs use ( + Src_Dirs_Root & "/hal/src/", -- From HAL config + Src_Dirs_Root & "/boards/stm32_common/nucleo_f401re/", -- From board definition + Src_Dirs_Root & "/boards/stm32_common/common/", -- From board definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm4f", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f401/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f401", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/dma/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/dma_interrupts/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/crc_stm32f4/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/i2c_stm32f4", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/power_control_stm32f4", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/uart_stm32f401/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/sd/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/STM32/drivers/sd/sdio/", -- From MCU definition + Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config + Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config + Src_Dirs_Root & "/middleware/src/utils", -- From middleware config + Src_Dirs_Root & "/middleware/src/audio", -- From middleware config + Src_Dirs_Root & "/middleware/src/monitor", -- From middleware config + Src_Dirs_Root & "/middleware/src/bitmap", -- From middleware config + Src_Dirs_Root & "/middleware/src/command_line", -- From middleware config + Src_Dirs_Root & "/middleware/src/sdmmc", -- From middleware config + Src_Dirs_Root & "/middleware/src/neopixel", -- From middleware config + Src_Dirs_Root & "/middleware/src/ravenscar-common", -- From middleware config + Src_Dirs_Root & "/components/src/**", -- From components config + "src/sfp/"); + + for Excluded_Source_Files use ( + "stm32-rng.ads", + "stm32-rng.adb", + "stm32-rng-interrupts.adb", + "stm32-rng-interrupts.ads", + "stm32-dac.ads", + "stm32-dac.adb", + "stm32-dcmi.ads", + "stm32-dcmi.adb", + "stm32-rng-polling.adb", + "stm32-rng-polling.ads" + ); + +end NUCLEO_F401RE_SFP; diff --git a/boards/nucleo_f401re/src/full/adl_config.ads b/boards/nucleo_f401re/src/full/adl_config.ads new file mode 100644 index 000000000..fa6e13b25 --- /dev/null +++ b/boards/nucleo_f401re/src/full/adl_config.ads @@ -0,0 +1,21 @@ +-- This package was generated by the Ada_Drivers_Library project wizard script +package ADL_Config is + Vendor : constant String := "STMicro"; -- From board definition + Max_Mount_Points : constant := 2; -- From default value + Max_Mount_Name_Length : constant := 128; -- From default value + Runtime_Profile : constant String := "ravenscar-sfp"; -- From command line + Device_Name : constant String := "STM32F401RE"; -- From board definition + Device_Family : constant String := "STM32F4"; -- From board definition + Has_Ravenscar_SFP_Runtime : constant String := "True"; -- From board definition + Runtime_Name : constant String := "ravenscar-sfp-nucleo_f401re"; -- From default value + Has_Ravenscar_Full_Runtime : constant String := "True"; -- From board definition + CPU_Core : constant String := "ARM Cortex-M4F"; -- From mcu definition + Board : constant String := "NUCLEO_F401RE"; -- From command line + Has_ZFP_Runtime : constant String := "False"; -- From board definition + Number_Of_Interrupts : constant := 0; -- From default value + High_Speed_External_Clock : constant := 8000000; -- From board definition + Use_Startup_Gen : constant Boolean := False; -- From command line + Max_Path_Length : constant := 1024; -- From default value + Runtime_Name_Suffix : constant String := "stm32f401"; -- From board definition + Architecture : constant String := "ARM"; -- From board definition +end ADL_Config; diff --git a/boards/nucleo_f401re/src/sfp/adl_config.ads b/boards/nucleo_f401re/src/sfp/adl_config.ads new file mode 100644 index 000000000..606176b9d --- /dev/null +++ b/boards/nucleo_f401re/src/sfp/adl_config.ads @@ -0,0 +1,21 @@ +-- This package was generated by the Ada_Drivers_Library project wizard script +package ADL_Config is + Vendor : constant String := "STMicro"; -- From board definition + Max_Mount_Points : constant := 2; -- From default value + Max_Mount_Name_Length : constant := 128; -- From default value + Runtime_Profile : constant String := "ravenscar-sfp"; -- From command line + Device_Name : constant String := "STM32F401RE"; -- From board definition + Device_Family : constant String := "STM32F4"; -- From board definition + Has_Ravenscar_SFP_Runtime : constant String := "True"; -- From board definition + Runtime_Name : constant String := "ravenscar-sfp-nucleo_f401re"; -- From default value + Has_Ravenscar_Full_Runtime : constant String := "True"; -- From board definition + CPU_Core : constant String := "ARM Cortex-M4F"; -- From mcu definition + Board : constant String := "NUCLEO_F401RE"; -- From command line + Has_ZFP_Runtime : constant String := "False"; -- From board definition + Number_Of_Interrupts : constant := 0; -- From default value + High_Speed_External_Clock : constant := 8000000; -- From board definition + Use_Startup_Gen : constant Boolean := False; -- From command line + Max_Path_Length : constant := 1024; -- From default value + Runtime_Name_Suffix : constant String := "nucleo_f401re"; -- From board definition + Architecture : constant String := "ARM"; -- From board definition +end ADL_Config; diff --git a/boards/stm32_common/nucleo_f401re/stm32-board.adb b/boards/stm32_common/nucleo_f401re/stm32-board.adb new file mode 100644 index 000000000..3501dcc01 --- /dev/null +++ b/boards/stm32_common/nucleo_f401re/stm32-board.adb @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2019, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4_discovery.c -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief This file provides set of firmware functions to manage Leds -- +-- and push-button available on STM32F42-Discovery Kit from -- +-- STMicroelectronics. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +package body STM32.Board is + + ------------------ + -- All_LEDs_Off -- + ------------------ + + procedure All_LEDs_Off is + begin + Clear (All_LEDs); + end All_LEDs_Off; + + ----------------- + -- All_LEDs_On -- + ----------------- + + procedure All_LEDs_On is + begin + Set (All_LEDs); + end All_LEDs_On; + + --------------------- + -- Initialize_LEDs -- + --------------------- + + procedure Initialize_LEDs is + begin + Enable_Clock (All_LEDs); + + Configure_IO + (All_LEDs, + (Mode_Out, + Resistors => Floating, + Output_Type => Push_Pull, + Speed => Speed_100MHz)); + end Initialize_LEDs; + + -------------------------------- + -- Configure_User_Button_GPIO -- + -------------------------------- + + procedure Configure_User_Button_GPIO is + begin + Enable_Clock (User_Button_Point); + Configure_IO (User_Button_Point, (Mode_In, Resistors => Floating)); + end Configure_User_Button_GPIO; + +end STM32.Board; diff --git a/boards/stm32_common/nucleo_f401re/stm32-board.ads b/boards/stm32_common/nucleo_f401re/stm32-board.ads new file mode 100644 index 000000000..a51b8ed9d --- /dev/null +++ b/boards/stm32_common/nucleo_f401re/stm32-board.ads @@ -0,0 +1,84 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2019, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- -- +-- This file is based on: -- +-- -- +-- @file stm32f4_discovery.h -- +-- @author MCD Application Team -- +-- @version V1.1.0 -- +-- @date 19-June-2014 -- +-- @brief This file contains definitions for STM32F4-Discovery Kit -- +-- LEDs, push-buttons hardware resources. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides declarations for devices on the STM32F4 Nucleo kits +-- manufactured by ST Microelectronics. + +with STM32.Device; use STM32.Device; +with STM32.GPIO; use STM32.GPIO; + +with Ada.Interrupts.Names; use Ada.Interrupts; + +package STM32.Board is + pragma Elaborate_Body; + + subtype User_LED is GPIO_Point; + + User_LED1 : User_LED renames PA5; + + LCH_LED : User_LED := User_LED1; + + All_LEDs : GPIO_Points := (1 => User_LED1); + + procedure Initialize_LEDs; + -- MUST be called prior to any use of the LEDs + + procedure Turn_On (This : in out User_LED) renames STM32.GPIO.Set; + procedure Turn_Off (This : in out User_LED) renames STM32.GPIO.Clear; + procedure Toggle (This : in out User_LED) renames STM32.GPIO.Toggle; + + procedure All_LEDs_Off with Inline; + procedure All_LEDs_On with Inline; + procedure Toggle_LEDs (These : in out GPIO_Points) + renames STM32.GPIO.Toggle; + + -- User button + + User_Button_Point : GPIO_Point renames PC13; + User_Button_Interrupt : constant Interrupt_ID := Names.EXTI15_10_Interrupt; + + procedure Configure_User_Button_GPIO; + -- Configures the GPIO port/pin for the blue user button. Sufficient + -- for polling the button, and necessary for having the button generate + -- interrupts. + +end STM32.Board; diff --git a/examples/nucleo_f401re/blinky_f401re.gpr b/examples/nucleo_f401re/blinky_f401re.gpr new file mode 100644 index 000000000..eb2081856 --- /dev/null +++ b/examples/nucleo_f401re/blinky_f401re.gpr @@ -0,0 +1,14 @@ +with "../../boards/nucleo_f401re/nucleo_f401re_full.gpr"; + +project Blinky_F401RE extends "../shared/common/common.gpr" is + + for Runtime ("Ada") use NUCLEO_F401RE_Full'Runtime("Ada"); + for Target use "arm-eabi"; + for Main use ("blinky.adb"); + for Languages use ("Ada"); + for Source_Dirs use ("../shared/hello_world_blinky/src"); + for Object_Dir use "../shared/hello_world_blinky/obj/nucleo_f401re"; + for Create_Missing_Dirs use "True"; + + package Compiler renames NUCLEO_F401RE_Full.Compiler; +end Blinky_F401RE; diff --git a/scripts/build_all_examples.py b/scripts/build_all_examples.py index 415ee3e7c..27944c6d0 100755 --- a/scripts/build_all_examples.py +++ b/scripts/build_all_examples.py @@ -106,6 +106,11 @@ def gprbuild(project_file, debug=False): "/examples/STM32F769_Discovery/dma2d_stm32f769disco.gpr", "/examples/STM32F769_Discovery/draw_stm32f769disco.gpr", + # NUCLEO-F401RE + "/boards/nucleo_f401re/nucleo_f401re_full.gpr", + "/boards/nucleo_f401re/nucleo_f401re_sfp.gpr", + "/examples/nucleo_f401re/blinky_f401re.gpr", + # NUCLEO-F446ZE "/boards/nucleo_f446ze/nucleo_f446ze_full.gpr", "/boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr",